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21. 发明申请

US20080082765A1 Resolving false dependencies of speculative load instructions 有权
标题翻译：解决投机负载指令的错误依赖
公开(公告)号：US20080082765A1
公开(公告)日：2008-04-03
申请号：US11541364
申请日：2006-09-29
申请人： Sebastien Hily , Zhongying Zhang , Per Hammarlund
发明人： Sebastien Hily , Zhongying Zhang , Per Hammarlund
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3834 , G06F12/1045
摘要： Methods and apparatus for resolving false dependencies associated with speculatively executing load instructions in a processor core are described. In one embodiment, physical addresses of a load operation and a store operation are compared in response to a determination that the load operation may be potentially dependent on the store operation. Other embodiments are also described.
摘要翻译：描述了用于解决与在处理器核心中推测性地执行加载指令相关联的错误依赖性的方法和装置。在一个实施例中，响应于负载操作可能潜在地依赖于存储操作的确定来比较加载操作和存储操作的物理地址。还描述了其它实施例。

22. 发明授权

US07130965B2 Apparatus and method for store address for store address prefetch and line locking 有权
标题翻译：用于存储地址预取和线路锁定的存储地址的装置和方法
公开(公告)号：US07130965B2
公开(公告)日：2006-10-31
申请号：US10743134
申请日：2003-12-23
申请人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
发明人： Per H. Hammarlund , Stephan Jourdan , Sebastien Hily , Aravindh Baktha , Hermann Gartler
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/3824 , G06F12/0831
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.
摘要翻译：本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或者从高速缓冲存储器中被逐出，则重置状态位。

23. 发明授权

US07752423B2 Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor 失效
标题翻译：通过在第一处理器中提交从推测性执行指令获得的结果来避免在第二处理器中执行指令
公开(公告)号：US07752423B2
公开(公告)日：2010-07-06
申请号：US09896526
申请日：2001-06-28
申请人： Haitham Akkary , Sebastien Hily
发明人： Haitham Akkary , Sebastien Hily
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/30072 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3857
摘要： A device is presented including a first processor and a second processor. A number of memory devices are connected to the first processor and the second processor. A register buffer is connected to the first processor and the second processor. A trace buffer is connected to the first processor and the second processor. A number of memory instruction buffers are connected to the first processor and the second processor. The first processor and the second processor perform single threaded applications using multithreading resources. A method is also presented where a first thread is executed from a first processor. The first thread is also executed from a second processor as directed by the first processor. The second processor executes instructions ahead of the first processor.
摘要翻译：呈现包括第一处理器和第二处理器的设备。多个存储器件连接到第一处理器和第二处理器。寄存器缓冲器连接到第一处理器和第二处理器。跟踪缓冲器连接到第一处理器和第二处理器。多个存储器指令缓冲器连接到第一处理器和第二处理器。第一个处理器和第二个处理器使用多线程资源执行单线程应用程序。还提出了一种从第一处理器执行第一线程的方法。如第一处理器所指示的那样，第一线程也从第二处理器执行。第二处理器在第一处理器之前执行指令。

24. 发明授权

US06591342B1 Memory disambiguation for large instruction windows 有权
标题翻译：大型指令窗口的内存消歧
公开(公告)号：US06591342B1
公开(公告)日：2003-07-08
申请号：US09461410
申请日：1999-12-14
申请人： Haitham Akkary , Sebastien Hily
发明人： Haitham Akkary , Sebastien Hily
IPC分类号： G06F1200
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction window of a processor. Some store queue entries include resolved store addresses, and some do not. The store forwarding buffer is a set-associative buffer that has entries allocated for store instructions as store addresses are resolved. Each entry in the store forwarding buffer is allocated into a set determined in part by a subset of the store address. When the set in the store forwarding buffer is full, an older entry in the set is discarded in favor of the newly allocated entry. A version count buffer including an array of overflow indicators is maintained to track overflow occurrences. As load addresses are resolved for load instructions in the instruction window, the set-associative store forwarding buffer can be searched to provide memory disambiguation.
摘要翻译：内存消歧设备包括存储队列，商店转发缓冲器和版本计数缓冲器。存储队列包括处理器的指令窗口中的每个存储指令的条目。一些存储队列条目包括解析的存储地址，有些不存在。商店转发缓冲区是一个集合关联缓冲区，具有分配给存储指令的条目，因为商店地址被解析。存储转发缓冲器中的每个条目被分配到部分由商店地址的子集确定的集合中。当存储转发缓冲区中的集合已满时，集合中的较旧条目被丢弃，有利于新分配的条目。包含一个溢出指示符阵列的版本计数缓冲器被保持以跟踪溢出事件。由于负载地址被解析为指令窗口中的加载指令，因此可以搜索设置关联的存储转发缓冲区以提供内存消歧。

25. 发明申请

US20140223105A1 METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING 有权
标题翻译：使用商店预购切割高级商店的方法和装置
公开(公告)号：US20140223105A1
公开(公告)日：2014-08-07
申请号：US13993508
申请日：2011-12-30
申请人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
发明人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0808 , G06F12/0862 , G06F2212/6028 , G06F2212/62
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
摘要翻译：根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

26. 发明授权

US07640419B2 Method for and a trailing store buffer for use in memory renaming 失效
标题翻译：用于存储器重命名的方法和后端存储缓冲区
公开(公告)号：US07640419B2
公开(公告)日：2009-12-29
申请号：US10743422
申请日：2003-12-23
申请人： Sebastien Hily , Per H. Hammarlund
发明人： Sebastien Hily , Per H. Hammarlund
IPC分类号： G06F9/30
CPC分类号： G06F9/3834
摘要： Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store address to a memory, and de-allocating the store address from the first storage, allocating the store address in a second storage, predicting a load instruction to be memory renamed, computing a load store source index, computing a load address, disambiguating the memory renamed load instruction, and retiring the memory renamed load instruction, if the store instruction is still allocated in at least one of the first storage and the second storage and should have effectively provided to the load the full data. The method may also include re-executing the load instruction without memory renaming, if the store instruction is not in at the first storage or in the second storage.
摘要翻译：本发明的实施例涉及一种能够实现高效存储器重命名的存储器管理方案和装置。该方法包括计算存储地址，将存储地址写入第一存储器中，将与存储地址相关联的数据写入存储器，以及从第一存储器解除存储地址，在第二存储器中分配存储地址，预测存储地址如果所述存储指令仍被分配在所述第一存储器中的至少一个中，则存储指令被重新命名为存储器重命名的加载指令，计算加载存储源索引，计算加载地址，消除所述存储器重命名的加载指令，以及退出所述存储器重命名加载指令，并且第二个存储应该有效地提供给负载的完整数据。如果存储指令不在第一存储器或第二存储器中，则该方法还可以包括重新执行加载指令而不进行存储器重命名。

27. 发明申请

US20080059723A1 Detecting and resolving locks in a memory unit 有权
标题翻译：检测和解决内存单元中的锁
公开(公告)号：US20080059723A1
公开(公告)日：2008-03-06
申请号：US11513636
申请日：2006-08-31
申请人： Prakash Math , Matthew Merten , Sebastien Hily , Beeman Strong , Morris Marden , David Burns
发明人： Prakash Math , Matthew Merten , Sebastien Hily , Beeman Strong , Morris Marden , David Burns
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F9/524
摘要： In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种具有第一计数器的装置，用于计数存储器单元中的高级请求的分配，耦合到存储器单元的处理器的计数周期的第二计数器以及耦合到第一和第二计数器根据至少一个计数器的值对高级请求执行一个或多个修复措施。描述和要求保护其他实施例。

28. 发明授权

US07590784B2 Detecting and resolving locks in a memory unit 有权
标题翻译：检测和解决内存单元中的锁
公开(公告)号：US07590784B2
公开(公告)日：2009-09-15
申请号：US11513636
申请日：2006-08-31
申请人： Prakash Math , Matthew Merten , Sebastien Hily , Beeman Strong , Morris Marden , David Burns
发明人： Prakash Math , Matthew Merten , Sebastien Hily , Beeman Strong , Morris Marden , David Burns
IPC分类号： G06F13/00
CPC分类号： G06F13/161 , G06F9/524
摘要： In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor coupled to the memory unit, and a controller coupled to the first and second counters to execute one or more one remediation measures with respect to the senior request based on a value of at least one of the counters. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种具有第一计数器的装置，用于计数存储器单元中的高级请求的分配，耦合到存储器单元的处理器的计数周期的第二计数器以及耦合到第一和第二计数器根据至少一个计数器的值对高级请求执行一个或多个修复措施。描述和要求保护其他实施例。

29. 发明授权

US07418552B2 Memory disambiguation for large instruction windows 失效
标题翻译：大型指令窗口的内存消歧
公开(公告)号：US07418552B2
公开(公告)日：2008-08-26
申请号：US10439203
申请日：2003-05-15
申请人： Haitham Akkary , Sebastien Hily
发明人： Haitham Akkary , Sebastien Hily
IPC分类号： G06F12/00
CPC分类号： G06F9/3824 , G06F9/3834
摘要： A memory disambiguation apparatus includes a store queue, a store forwarding buffer, and a version count buffer. The store queue includes an entry for each store instruction in the instruction window of a processor. Some store queue entries include resolved store addresses, and some do not. The store forwarding buffer is a set-associative buffer that has entries allocated for store instructions as store addresses are resolved. Each entry in the store forwarding buffer is allocated into a set determined in part by a subset of the store address. When the set in the store forwarding buffer is full, an older entry in the set is discarded in favor of the newly allocated entry. A version count buffer including an array of overflow indicators is maintained to track overflow occurrences. As load addresses are resolved for load instructions in the instruction window, the set-associative store forwarding buffer can be searched to provide memory disambiguation.
摘要翻译：内存消歧设备包括存储队列，商店转发缓冲器和版本计数缓冲器。存储队列包括处理器的指令窗口中的每个存储指令的条目。一些存储队列条目包括解析的存储地址，有些不存在。商店转发缓冲区是一个集合关联缓冲区，具有分配给存储指令的条目，因为商店地址被解析。存储转发缓冲器中的每个条目被分配到部分由商店地址的子集确定的集合中。当存储转发缓冲区中的集合已满时，集合中的较旧条目被丢弃，有利于新分配的条目。包含一个溢出指示符阵列的版本计数缓冲器被保持以跟踪溢出事件。由于负载地址被解析为指令窗口中的加载指令，因此可以搜索设置关联的存储转发缓冲区以提供内存消歧。

30. 发明授权

US09405545B2 Method and apparatus for cutting senior store latency using store prefetching 有权
标题翻译：使用存储预取来切割高级存储延迟的方法和装置
公开(公告)号：US09405545B2
公开(公告)日：2016-08-02
申请号：US13993508
申请日：2011-12-30
申请人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
发明人： Stanislav Shwartsman , Melih Ozgul , Sebastien Hily , Shlomo Raikin , Raanan Sade , Ron Shalev
IPC分类号： G06F12/08 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0808 , G06F12/0862 , G06F2212/6028 , G06F2212/62
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
摘要翻译：根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

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