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21. 发明授权

US06256219B1 Integrated memory having memory cells disposed at crossover points of word lines and bit lines 失效
标题翻译：具有位于字线和位线的交叉点处的存储单元的集成存储器
公开(公告)号：US06256219B1
公开(公告)日：2001-07-03
申请号：US09589439
申请日：2000-06-07
申请人： Peter Schrögmeier , Stefan Dietrich , Sabine Schöniger , Christian Weis
发明人： Peter Schrögmeier , Stefan Dietrich , Sabine Schöniger , Christian Weis
IPC分类号： G11C506
CPC分类号： G11C11/4096 , G11C7/1006
摘要： An integrated memory has first control lines, which run in the direction of bit lines, and a second control line, which runs in the direction of word lines. First control inputs of in each case at least two switching elements that are connected to different sense amplifiers are connected to the same first control line. The second control inputs of the switching elements are connected to the second control line. The invention makes it possible to reduce the number of first control lines running in the direction of the bit lines.
摘要翻译：集成存储器具有沿位线方向延伸的第一控制线和沿字线方向延伸的第二控制线。在每种情况下，连接到不同读出放大器的至少两个开关元件的第一控制输入连接到相同的第一控制线。开关元件的第二控制输入连接到第二控制线。本发明可以减少在位线的方向上行进的第一控制线的数量。

22. 发明授权

US06819624B2 Latency time circuit for an S-DRAM 失效
标题翻译： S-DRAM的延迟时间电路
公开(公告)号：US06819624B2
公开(公告)日：2004-11-16
申请号：US10249029
申请日：2003-03-11
申请人： Pramod Acharya , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier
发明人： Pramod Acharya , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , H03L7/0814
摘要： Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.
摘要翻译： S-DRAM的延迟时间电路，其由高频时钟信号计时，用于产生用于通过S-DRAM的数据路径进行同步数据传输的延迟数据使能控制信号，具有至少一个可控延迟时间发生器，用于延迟具有可调延迟时间的解码数据使能控制信号，其特征在于至少一个比较电路，该比较电路将高频时钟信号的周期时间与预定的解码时间进行比较，以及通过信号延迟电路可以被接通比较电路的装置，以便在预定的延迟时间延迟解码的数据使能控制信号，其中当时钟信号的周期时间处于限制时间区域时，信号延迟电路被比较电路接通位于预定的解码时间。

23. 发明授权

US06731567B2 DDR memory and storage method 有权
标题翻译： DDR内存和存储方式
公开(公告)号：US06731567B2
公开(公告)日：2004-05-04
申请号：US10350482
申请日：2003-01-24
申请人： Pramod Acharya , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier
发明人： Pramod Acharya , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1006 , G11C11/4093 , G11C2207/107
摘要： The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.
摘要翻译：本发明涉及DDR存储器和存储方法，用于将数据存储在具有多个存储单元的DDR存储器中，每个存储器单元具有规定的字长，其中使用串行数据输入来读取串行数据上升或数据时钟信号的下降沿和串行 - 并行转换器用于将从读取的数据中的规定数量的数据项组合在一起，以从具有规定字长的数据字中给出规定数量的字。为了传送数据从一个同步区域到另一个同步区域，并且其再同步更可靠，本发明涉及一种接收存储器，该接口存储器在接收到与数据块信号同步的复制信号时从串行 - 并行转换器复制至少一个数据字并在接收到与系统时钟信号同步的输出信号时将其输出到总线。

24. 发明授权

US06188642B1 Integrated memory having column decoder for addressing corresponding bit line 失效
标题翻译：具有用于寻址相应位线的列解码器的集成存储器
公开(公告)号：US06188642B1
公开(公告)日：2001-02-13
申请号：US09348736
申请日：1999-07-06
申请人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
发明人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.
摘要翻译：集成存储器具有用于解码列地址并用于寻址对应位线的列解码器。存储器还具有第一列地址总线，其用于将第一列地址传送到列解码器，以及第二列地址总线，其用于将第二列地址传送到列解码器。列解码器在每种情况下都对应于提供给它的第一列地址和第二列地址的位线。

25. 发明授权

US07363561B2 Method and circuit arrangement for resetting an integrated circuit 有权
标题翻译：用于复位集成电路的方法和电路装置
公开(公告)号：US07363561B2
公开(公告)日：2008-04-22
申请号：US11117736
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Peter Schrögmeier
IPC分类号： G01R31/28
CPC分类号： G06F1/24 , H03K5/1534
摘要： The invention relates to a method for resetting at least one circuit part of an integrated circuit, in particular a synchronous semiconductor memory, in which a clock signal and a clock signal that is inverted with respect to the latter are provided in order to clock the integrated circuit, and in which, when a reset condition is present, an item of reset information is coded onto the clock signal or onto the inverted clock signal. The invention also relates to a circuit arrangement for carrying out the method according to the invention, having a clock suppression device and a decoder circuit, which is intended to extract the reset information from the clock signal or from the inverted clock signal.
摘要翻译：本发明涉及一种用于复位集成电路，特别是同步半导体存储器的至少一个电路部分的方法，其中提供时钟信号和相对于后者反相的时钟信号，以便对集成电路电路，并且当存在复位条件时，将复位信息的项目编码到时钟信号或反相时钟信号上。本发明还涉及用于执行根据本发明的方法的电路装置，其具有时钟抑制装置和解码器电路，其用于从时钟信号或反相时钟信号中提取复位信息。

26. 发明授权

US06401224B1 Integrated circuit and method for testing it 有权
标题翻译：集成电路及其测试方法
公开(公告)号：US06401224B1
公开(公告)日：2002-06-04
申请号：US09261100
申请日：1999-03-02
申请人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich
发明人： Sabine Schöniger , Peter Schrögmeier , Thomas Hein , Stefan Dietrich
IPC分类号： G01R3128
CPC分类号： G01R31/3185
摘要： A test method suitable for testing at least one integrated circuit which, on a main area, has contact areas that serve to transfer signals during a first operating mode of the circuit. Only some of the contact areas are contact-connected to test contacts of a test apparatus and the circuit is put into a second operating mode in which the signals which are transferred via at least one of the non-contact-connected contact areas in the first operating mode are transferred via at least one of the contact-connected contact areas.
摘要翻译：一种适用于测试至少一个集成电路的测试方法，该集成电路在主区域具有用于在电路的第一操作模式期间传送信号的接触区域。只有一些接触区域接触连接到测试装置的测试触点，并且电路进入第二操作模式，其中通过第一操作模式中的至少一个非接触连接的接触区域传送的信号操作模式通过至少一个接触连接的接触区域传送。

27. 发明授权

US06388944B2 Memory component with short access time 有权
标题翻译：具有访问时间短的内存组件
公开(公告)号：US06388944B2
公开(公告)日：2002-05-14
申请号：US09773221
申请日：2001-01-31
申请人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
发明人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C7/1069
摘要： A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.
摘要翻译：具有短数据访问时间的存储器芯片通过相对于单元阵列条的中心对中开关来限制远离输出放大器的本地数据线条上的位的传播时间，其中开关是本地数据线和主数据线。

28. 发明授权

US07224625B2 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US07224625B2
公开(公告)日：2007-05-29
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

29. 发明申请

US20050254307A1 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US20050254307A1
公开(公告)日：2005-11-17
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C11/34 , G11C11/407 , G11C11/4076 , G11C11/4096
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

30. 发明授权

US07848134B2 FB DRAM memory with state memory 有权
标题翻译： FB DRAM内存带状态存储器
公开(公告)号：US07848134B2
公开(公告)日：2010-12-07
申请号：US12178407
申请日：2008-07-23
申请人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
发明人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/404 , G11C2211/4016
摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.
摘要翻译：公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

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