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21. 发明申请

US20080263228A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20080263228A1
公开(公告)日：2008-10-23
申请号：US12151390
申请日：2008-05-05
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F3/00
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

22. 发明授权

US5930523A Microcomputer having multiple bus structure coupling CPU to other processing elements 失效
标题翻译：微型计算机具有多个总线结构，将CPU耦合到其他处理元件
公开(公告)号：US5930523A
公开(公告)日：1999-07-27
申请号：US055099
申请日：1998-04-03
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F13/28 , G06F9/30 , G06F9/302 , G06F9/38 , G06F12/00 , G06F12/08 , G06F13/36 , G06F13/40 , G06F15/78 , H04L12/28 , G06F15/76
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02B60/1207 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

23. 发明授权

US06351788B1 Data processor and data processing system 失效
标题翻译：数据处理器和数据处理系统
公开(公告)号：US06351788B1
公开(公告)日：2002-02-26
申请号：US09297310
申请日：1999-06-10
申请人： Takanaga Yamazaki , Yasushi Akao , Keiichi Kurakazu , Masayasu Ohizumi , Takeshi Kataoka , Tatsuo Nakai , Mitsuhiro Miyazaki , Yosuke Murayama
发明人： Takanaga Yamazaki , Yasushi Akao , Keiichi Kurakazu , Masayasu Ohizumi , Takeshi Kataoka , Tatsuo Nakai , Mitsuhiro Miyazaki , Yosuke Murayama
IPC分类号： G06F1300
CPC分类号： G06F12/0864
摘要： A data processor including a central processing unit and a plurality of direct map cache memories (3, 4) has a plurality of area designating circuits (5, 6) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.
摘要翻译：包括中央处理单元和多个直接地图高速缓存存储器（3,4）的数据处理器具有多个区域指定电路（5,6），用于可变地指定存储器空间中的地址区域的位置和大小来管理中央处理单元并且部分地重叠由多个区域指定电路指定的地址区域。因此，重叠区域（Eco）具有与多个高速缓存存储器组合的2路组合关联高速缓冲存储器的功能。对于非重叠区域，各个高速缓冲存储器用作直接映射高速缓冲存储器。先前通过安排哪个处理例程到达哪个地址区域，然后以什么处理速度执行这种例程，以前被判定为获得必要的数据处理能力。因此，当将高速缓存对象区域分配给多个高速缓冲存储器时，将多个高速缓存存储器组合为用于操作的组关联高速缓存，特别需要高速操作或数据。因此，可以通过提高必要区域的缓存命中率来优化系统。

24. 发明授权

US5293586A Data processing system for development of outline fonts 失效
标题翻译：数据处理系统用于开发大纲字体
公开(公告)号：US5293586A
公开(公告)日：1994-03-08
申请号：US958610
申请日：1992-10-08
申请人： Takanaga Yamazaki , Shiro Baba , Keiichi Kurakazu , Masaharu Ando , Toshio Tanaka , Susumu Kaneko
发明人： Takanaga Yamazaki , Shiro Baba , Keiichi Kurakazu , Masaharu Ando , Toshio Tanaka , Susumu Kaneko
IPC分类号： G06K15/02 , G06T11/20 , G09G5/24 , G09G5/393 , G06F15/62
CPC分类号： G09G5/393 , G06K15/02 , G06T11/203 , G09G5/24 , G06K2215/0045
摘要： A single chip microcomputer formed on a semiconductor substrate includes a central processing unit, a ROM storing therein a program for operating the central processing unit, a digital signal processor, and a multi-port RAM. The digital signal processor develops an outline font on the multi-port RAM in accordance with a program stored in a storage unit provided in the digital signal processor. This eliminates the necessity of development of an outline font by the central processing unit and allows high speed execution of such development of an outline font. Further, the central processing unit and the digital signal processor can operate in a parallel relationship.
摘要翻译：形成在半导体基板上的单芯片微计算机包括中央处理单元，存储有用于操作中央处理单元的程序的ROM，数字信号处理器和多端口RAM。数字信号处理器根据存储在数字信号处理器中的存储单元中的程序，在多端口RAM上形成轮廓字体。这消除了由中央处理单元开发轮廓字体的必要性，并允许高速执行轮廓字体的这种开发。此外，中央处理单元和数字信号处理器可以并行运行。

25. 发明授权

US5450610A RISC system capable of performing calls and returns without advancing or restoring window pointers 失效
标题翻译： RISC系统能够执行调用和返回，而无需前进或恢复窗口指针
公开(公告)号：US5450610A
公开(公告)日：1995-09-12
申请号：US183830
申请日：1994-01-21
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Thoru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Thoru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating the main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在相同的指令中提供了用于指定主存储器的地址部分。

26. 发明授权

US5307502A Data processing system having multiple register management for call and return operations 失效
标题翻译：数据处理系统具有多个用于呼叫和返回操作的寄存器管理
公开(公告)号：US5307502A
公开(公告)日：1994-04-26
申请号：US945930
申请日：1992-09-17
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing. Besides, an address part for designating main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在同一指令中提供了用于指定主存储器的地址部分。

27. 发明授权

US5517664A RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing 失效
标题翻译：具有指令的RISC系统，其包括用于在处理期间访问存储在寄存器中的数据的寄存器区域和位移部分
公开(公告)号：US5517664A
公开(公告)日：1996-05-14
申请号：US459965
申请日：1995-06-02
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.Besides, an address part for designating the main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在相同的指令中提供了用于指定主存储器的地址部分。

28. 发明授权

US5214786A RISC system performing calls and returns without saving or restoring window pointers and delaying saving until multi-register areas are filled 失效
标题翻译： RISC系统执行调用和返回，而不保存或恢复窗口指针，并延迟保存，直到填充多个寄存器区域
公开(公告)号：US5214786A
公开(公告)日：1993-05-25
申请号：US37843
申请日：1987-04-13
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Thoru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Thoru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.Besides, an address part for designating the main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在相同的指令中提供了用于指定主存储器的地址部分。

29. 发明授权

US5070473A Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US5070473A
公开(公告)日：1991-12-03
申请号：US77442
申请日：1987-07-24
申请人： Makoto Takano , Yasuhiko Hoshi , Keiichi Kurakazu , Shiro Baba
发明人： Makoto Takano , Yasuhiko Hoshi , Keiichi Kurakazu , Shiro Baba
IPC分类号： G06F13/28 , G06F13/42
CPC分类号： G06F13/4213
摘要： A wait signal formed by a program wait circuit incorporated in a microprocessor is transmitted to outside circuitry, such as a slave microprocessor or a direct memory access control device. Thereby an outside device assumes the functions of bus master which is incorporated into a wait operation for access to a memory unit. With such a construction, a microcomputer system comprising a plurality of devices to be made into a bus mask can be simplified.
摘要翻译：由并入微处理器的程序等待电路形成的等待信号被发送到诸如从微处理器或直接存储器存取控制装置的外部电路。因此，外部设备承担总线主控器的功能，其被并入到用于访问存储器单元的等待操作中。通过这样的结构，可以简化包括要制成总线掩模的多个装置的微计算机系统。

30. 发明授权

US5493659A Data processor providing fast break in program execution 失效
标题翻译：数据处理器在程序执行中提供快速突破
公开(公告)号：US5493659A
公开(公告)日：1996-02-20
申请号：US626740
申请日：1990-12-13
申请人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
发明人： Keiichi Kurakazu , Yoshikazu Aoto , Shiro Baba , Satoshi Masuda , Hiroyuki Kida , Shinji Kawashima , Yoshiaki Naruse
IPC分类号： G06F11/36 , G06F9/44 , G06F9/46
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program execution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.
摘要翻译：在处理器中设置有响应于外部提供的信号切换输入存储电路中保持的SWI指令的电路，由此可以使用这样的内部电路来实现对程序字的替换，从而高速并且可以实现程序执行的可靠中断。此外，通过设置指定的操作模式来建立与正常中断分离的中断功能，由此当使用数据处理器作为仿真器时，可以通过利用特殊中断来容易地实现包括普通中断处理的用户程序的中断功能。此外，通过附加地提供表示中断状态的信号的功能，可以简化外部电路。

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