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21. 发明授权

US08525184B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08525184B2
公开(公告)日：2013-09-03
申请号：US13531279
申请日：2012-06-22
申请人： Masaya Okada , Makato Kiyama , Seiji Yaegashi , Ken Nakata
发明人： Masaya Okada , Makato Kiyama , Seiji Yaegashi , Ken Nakata
IPC分类号： H01L29/15
CPC分类号： H01L29/8725 , H01L21/8252 , H01L27/0605 , H01L27/0727 , H01L29/0692 , H01L29/2003 , H01L29/7786 , H01L29/7788 , H01L29/7789 , H01L29/8128 , H01L29/872
摘要： There are provided a semiconductor device that includes a bypass protection unit against surge voltage or the like, achieves good withstand voltage characteristics and low on-resistance (low On-state voltage), has a simple structure, and is used for large-current purpose and a method for producing the semiconductor device.In the present invention, the semiconductor device includes an n+-type GaN substrate 1 having a GaN layer that is in ohmic contact with a supporting substrate, a FET having an n−-type GaN drift layer 2 in a first region R1, and an SBD having an anode electrode in a second region R2, the anode electrode being in Schottky contact with the d−-type GaN drift layer 2. The FET and the SBD are arranged in parallel. A drain electrode D of the FET and a cathode electrode C of the SBD are formed on the back of the n+-type GaN substrate 1.
摘要翻译：提供了一种具有抗浪涌电压等的旁路保护单元的半导体器件，具有良好的耐压特性和低导通电阻（低导通电压），结构简单，用于大电流目的以及半导体装置的制造方法。在本发明中，半导体器件包括具有与支撑衬底欧姆接触的GaN层的n +型GaN衬底1，在第一区域R1中具有n型GaN漂移层2的FET和 SBD在第二区域R2中具有阳极电极，阳极与d型GaN漂移层2肖特基接触.FET和SBD平行布置。 FET的漏电极D和SBD的阴极电极C形成在n +型GaN衬底1的背面。

22. 发明授权

US08729562B2 Semiconductor device and method for manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08729562B2
公开(公告)日：2014-05-20
申请号：US13498767
申请日：2010-06-24
申请人： Masaya Okada , Makoto Kiyama
发明人： Masaya Okada , Makoto Kiyama
IPC分类号： H01L29/15
CPC分类号： H01L29/7786 , H01L29/0891 , H01L29/2003 , H01L29/66462 , H01L29/7788 , H01L29/7789
摘要： There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 15 having an opening 28, a regrown layer 27 including a channel, a gate electrode G, a source electrode S, and a drain electrode D. The regrown layer 27 includes an electron transit layer 22 and an electron supply layer 26. The GaN-based layered body includes a p-type GaN layer 6 whose end surface is covered by the regrown layer in the opening, and a p-side electrode 11 that is in ohmic contact with the p-type GaN layer is disposed.
摘要翻译：提供了具有低导通电阻，高迁移率和良好的夹断特性的高电流半导体器件，并且即使漏极电压增加也不容易引起扭结现象，并且制造半导体器件的方法。本发明的半导体器件包括具有开口28的GaN基层叠体15，包括沟道的再生长层27，栅电极G，源电极S和漏电极D.再生层27包括：电子转移层22和电子供给层26.该GaN基层叠体包括端面被开口部中的再生长层覆盖的p型GaN层6和与欧姆接触的p侧电极11 配置p型GaN层。

23. 发明授权

US08405125B2 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08405125B2
公开(公告)日：2013-03-26
申请号：US12966306
申请日：2010-12-13
申请人： Masaya Okada , Makoto Kiyama
发明人： Masaya Okada , Makoto Kiyama
IPC分类号： H01L29/66 , H01L21/338
CPC分类号： H01L29/7787 , H01L29/045 , H01L29/0657 , H01L29/2003 , H01L29/66462 , H01L29/7788 , H01L29/7789
摘要： The semiconductor device includes a GaN-based layered body having an opening and including an n-type drift layer and a p-type layer located on the n-type drift layer, a regrown layer including a channel and located so as to cover the opening, and a gate electrode located on the regrown layer and formed along the regrown layer, wherein the opening reaches the n-type drift layer, and an edge of the gate electrode is not located outside a region of the p-type layer when viewed in plan.
摘要翻译：半导体器件包括具有开口并且包括n型漂移层和位于n型漂移层上的p型层的GaN基层状体，包括沟道并且被覆盖开口的再生长层以及位于再生长层上并沿着再生长层形成的栅电极，其中开口到达n型漂移层，并且当从p型层中观察时，栅电极的边缘不位于p型层的区域的外侧计划。

24. 发明申请

US20120181548A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120181548A1
公开(公告)日：2012-07-19
申请号：US13498767
申请日：2010-06-24
申请人： Masaya Okada , Makoto Kiyama
发明人： Masaya Okada , Makoto Kiyama
IPC分类号： H01L29/778 , H01L21/20
CPC分类号： H01L29/7786 , H01L29/0891 , H01L29/2003 , H01L29/66462 , H01L29/7788 , H01L29/7789
摘要： There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 15 having an opening 28, a regrown layer 27 including a channel, a gate electrode G, a source electrode S, and a drain electrode D. The regrown layer 27 includes an electron transit layer 22 and an electron supply layer 26. The GaN-based layered body includes a p-type GaN layer 6 whose end surface is covered by the regrown layer in the opening, and a p-side electrode 11 that is in ohmic contact with the p-type GaN layer is disposed.
摘要翻译：提供了具有低导通电阻，高迁移率和良好的夹断特性的高电流半导体器件，并且即使漏极电压增加也不容易引起扭结现象，并且制造半导体器件的方法。本发明的半导体器件包括具有开口28的GaN基层叠体15，包括沟道的再生长层27，栅电极G，源电极S和漏电极D.再生层27包括：电子转移层22和电子供给层26.该GaN基层叠体包括端面被开口部中的再生长层覆盖的p型GaN层6和与欧姆接触的p侧电极11 配置p型GaN层。

25. 发明申请

US20100183112A1 METHOD OF MANUFACTURING CORE SHROUD FOR NUCLEAR POWER PLANT AND STRUCTURE OF NUCLEAR POWER PLANT 有权
标题翻译：核电厂核心裂缝及核电厂结构的制造方法
公开(公告)号：US20100183112A1
公开(公告)日：2010-07-22
申请号：US12646519
申请日：2009-12-23
申请人： Eiji ASHIDA , Xudong Zhang , Shoh Tarasawa , Masaya Okada , Yusuke Anma
发明人： Eiji ASHIDA , Xudong Zhang , Shoh Tarasawa , Masaya Okada , Yusuke Anma
IPC分类号： G21C11/08 , B23K35/38 , B23K26/28
CPC分类号： B23K33/006 , B23K26/28 , B23K35/22 , B23K35/38 , G21C11/083 , G21C21/00 , Y02E30/40
摘要： The present invention provides a method of manufacturing a core shroud for a nuclear plant and a nuclear power plant structure in which a groove portion is easily assembled in the case of manufacturing the core shroud having a weld structure of a nuclear power plant by a laser welding, and it is possible to obtain a weld joint portion in which a plastic distortion region and a residual stress are as small as possible, going with a solidification shrinkage of the weld portion. At a time of welding butted portions of a plurality of members constructing a core shroud, a root face is provided in the butted portion, a length of the root face is set to 25% to 95% of a thickness of the thinner one of the butted portions of a plurality of members, a narrow groove is provided in the other than the root face, and the butted portions are welded by a laser welding using a weld wire.
摘要翻译：本发明提供一种制造用于核电厂的核心护罩的方法和核电站结构，其中在通过激光焊接制造具有核电厂的焊接结构的芯护罩的情况下容易组装槽部，并且可以获得其中塑性变形区域和残余应力尽可能小的焊接接头部分，随着焊接部分的凝固收缩。在构成芯护罩的多个构件的对接部分的焊接时，在对接部设置有根面，根面的长度设定为较薄的一个的厚度的25％〜95％多个构件的对接部分，在根面上设置有窄槽，并且通过使用焊丝的激光焊接焊接对接部。

26. 发明授权

US08681923B2 Method of manufacturing core shroud for nuclear power plant and structure of nuclear power plant 有权
标题翻译：制造核电厂核心护栏和核电站结构的方法
公开(公告)号：US08681923B2
公开(公告)日：2014-03-25
申请号：US12646519
申请日：2009-12-23
申请人： Eiji Ashida , Xudong Zhang , Shoh Tarasawa , Masaya Okada , Yusuke Anma
发明人： Eiji Ashida , Xudong Zhang , Shoh Tarasawa , Masaya Okada , Yusuke Anma
IPC分类号： B23K26/20 , B23K26/12 , G21C21/00 , G21C5/02 , G21C11/00 , B23K26/00 , G21C5/00
CPC分类号： B23K33/006 , B23K26/28 , B23K35/22 , B23K35/38 , G21C11/083 , G21C21/00 , Y02E30/40
摘要： The present invention provides a method of manufacturing a core shroud for a nuclear plant and a nuclear power plant structure in which a groove portion is easily assembled in the case of manufacturing the core shroud having a weld structure of a nuclear power plant by a laser welding, and it is possible to obtain a weld joint portion in which a plastic distortion region and a residual stress are as small as possible, going with a solidification shrinkage of the weld portion. At a time of welding butted portions of a plurality of members constructing a core shroud, a root face is provided in the butted portion, a length of the root face is set to 25% to 95% of a thickness of the thinner one of the butted portions of a plurality of members, a narrow groove is provided in the other than the root face, and the butted portions are welded by a laser welding using a weld wire.
摘要翻译：本发明提供一种制造用于核电厂的核心护罩的方法和核电站结构，其中在通过激光焊接制造具有核电厂的焊接结构的芯护罩的情况下容易组装槽部分，并且可以获得其中塑性变形区域和残余应力尽可能小的焊接接头部分，随着焊接部分的凝固收缩。在构成芯护罩的多个构件的对接部分的焊接时，在对接部设置有根面，根面的长度设定为较薄的一个的厚度的25％〜95％多个构件的对接部分，在根面上设置有窄槽，并且通过使用焊丝的激光焊接焊接对接部。

27. 发明授权

US5828619A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5828619A
公开(公告)日：1998-10-27
申请号：US635869
申请日：1996-04-18
申请人： Hiroshige Hirano , Masaya Okada
发明人： Hiroshige Hirano , Masaya Okada
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： In a DRAM, an external cycle count circuit detects an operation cycle of a signal RAS which is externally inputted, and a signal expressing the result is outputted to a CBR signal generating circuit and a self refresh signal generating circuit. In response to outputs from the respective signal generating circuits, an internal RAS signal generating circuit outputs a refresh instruction signal INRAS for CBR refresh and self refresh. For self refresh, as the operation cycle of the signal RAS immediately before self refresh begins, a refresh cycle is set longer. For CBR refresh, when the operation cycle of the signal RAS is long, a CBR refresh instruction signal is generated in accordance with only a part of an operation of the signal RAS. By reducing the frequency of refresh, consumption power is reduced. By means of control which considers a parameter which influences an internal temperature of a semiconductor memory device such as a DRAM, consumption power is reduced and an operation speed is improved.
摘要翻译：在DRAM中，外部周期计数电路检测外部输入的信号RAS的操作周期，并将表示结果的信号输出到CBR信号生成电路和自刷新信号生成电路。响应于各信号发生电路的输出，内部RAS信号发生电路输出用于CBR刷新和自刷新的刷新指令信号INRAS。对于自刷新，随着自刷新开始之前的信号RAS的操作周期，刷新周期被设置得更长。对于CBR刷新，当信号RAS的操作周期长时，根据信号RAS的一部分操作产生CBR刷新指令信号。通过降低刷新频率，降低功耗。通过考虑影响诸如DRAM的半导体存储器件的内部温度的参数的控制，消耗功率降低，并且提高了操作速度。

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