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21. 发明授权

US06809419B2 Semiconductor device 有权
公开(公告)号：US06809419B2
公开(公告)日：2004-10-26
申请号：US10411118
申请日：2003-04-11
申请人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
发明人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10162 , H01L2924/1306 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

22. 发明授权

US06721774B1 Low power multiplier 失效
标题翻译：低功率乘法器
公开(公告)号：US06721774B1
公开(公告)日：2004-04-13
申请号：US09074197
申请日：1998-05-07
申请人： Wai Lee , Toshiyuki Sakuta
发明人： Wai Lee , Toshiyuki Sakuta
IPC分类号： G06F752
CPC分类号： G06F7/5338 , G06F2207/3884
摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.
摘要翻译：数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号，至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些加法器电路。

23. 发明授权

US5453959A Semiconductor memory device having a self-refreshing control circuit 失效
标题翻译：具有自刷新控制电路的半导体存储器件
公开(公告)号：US5453959A
公开(公告)日：1995-09-26
申请号：US220249
申请日：1994-03-30
申请人： Toshiyuki Sakuta , Tomohiro Suzuki
发明人： Toshiyuki Sakuta , Tomohiro Suzuki
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device capable of a self-refreshing operation with a refresh-initiation signal generated in the memory device has a self-refreshing control circuit. A self-refreshing operation is automatically effected, without externally supplied clock signals, with a specific refreshing cycle having an internally set mode entry time period, a burst refresh time period and an internally set pause time period. These time periods are detected by a single counter circuit arranged to count pulses produced from a basic clock pulse signal generated by an oscillator. The burst refreshing is effected with the pulses contained in a pulse signal generated in synchronization with the basic clock pulse signal from the oscillator.
摘要翻译：能够在存储装置中产生的刷新启动信号进行自刷新操作的半导体存储器件具有自刷新控制电路。在没有外部提供的时钟信号的情况下，自动刷新操作具有具有内部设定模式进入时间段，突发刷新时间周期和内部设置的暂停时间段的特定刷新周期。这些时间周期通过一个单个计数器电路来检测，该计数器电路被布置成对由振荡器产生的基本时钟脉冲信号产生的脉冲进行计数。脉冲串刷新通过与来自振荡器的基本时钟脉冲信号同步产生的脉冲信号中包含的脉冲来实现。

24. 发明授权

US07005906B2 Semiconductor integrated-circuit device and method to speed-up CMOS circuit 失效
标题翻译：半导体集成电路器件及方法，加速CMOS电路
公开(公告)号：US07005906B2
公开(公告)日：2006-02-28
申请号：US10781746
申请日：2004-02-20
申请人： Nao Miyamoto , Toshiyuki Sakuta
发明人： Nao Miyamoto , Toshiyuki Sakuta
IPC分类号： G06F1/04 , G06F9/45
CPC分类号： G11C7/1057 , G06F17/505 , G11C7/1051 , H01L27/0207 , H01L27/11807
摘要： The present invention provides a semiconductor integrated-circuit device capable of achieving higher-density integration and faster operation, and a CMOS circuit operational speeding-up method for easily achieving the operating speeds of CMOS circuits, including existing one.A signal transferring path includes a plurality of CMOS-constructed logic gate circuits provided between one pair of flip-flop circuits for acquiring and holding signals by use of clock signals. The signal transferring path includes a first and a second signal transferring path. The first signal transferring path is constituted by enhancement-type MOSFETs and has a signal transferring delay time equal to, or less than, a permissible signal transferring delay time. The second signal transferring path is configured such that, among the above-mentioned plurality of logic gate circuits, a logic gate circuit having a delay time longer than the above-mentioned permissible signal transferring delay time when constituted using enhancement-type MOSFETs is replaced with a depletion-type MOSFET so that the second signal transferring path may provide a signal transferring delay time equal to or less than the permissible signal transferring delay time mentioned above.
摘要翻译：本发明提供一种能够实现更高密度集成和更快速运行的半导体集成电路器件，以及用于容易地实现包含现有CMOS电路的CMOS电路的工作速度的CMOS电路运行加速方法。

25. 发明授权

US06553439B1 Remote configuration access for integrated circuit devices 有权
标题翻译：集成电路设备的远程配置访问
公开(公告)号：US06553439B1
公开(公告)日：2003-04-22
申请号：US09385390
申请日：1999-08-30
申请人： Michael J. Greger , Eric R. Wehage , Toshiyuki Sakuta
发明人： Michael J. Greger , Eric R. Wehage , Toshiyuki Sakuta
IPC分类号： G06F1314
CPC分类号： G06F13/4291
摘要： A local integrated circuit device provides remote configuration access to one or more remote integrated circuit devices. The local integrated circuit device receives configuration access requests through at least two interfaces. The local integrated circuit device accesses a configuration space of one or more remote integrated circuit devices in accordance with the received configuration access requests.
摘要翻译：本地集成电路设备提供对一个或多个远程集成电路设备的远程配置访问。本地集成电路设备通过至少两个接口接收配置访问请求。本地集成电路设备根据接收到的配置访问请求访问一个或多个远程集成电路设备的配置空间。

26. 发明授权

US5534817A Voltage generating circuit 失效
标题翻译：电压发生电路
公开(公告)号：US5534817A
公开(公告)日：1996-07-09
申请号：US292538
申请日：1994-08-18
申请人： Tomohiro Suzuki , Toshiyuki Sakuta
发明人： Tomohiro Suzuki , Toshiyuki Sakuta
IPC分类号： G01R19/00 , G05F3/24 , G05F3/26 , G11C11/407 , H03G3/02 , H03K19/00 , G05F3/02
CPC分类号： G05F3/247 , G05F3/262
摘要： A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly. By virtue of a large amount of current flowing to the output side of a terminal side, namely the load circuit side, at an appropriate voltage from a power source terminal 18 via p-type MOS transistor MP6A which was turned on in the saturated area, a reduction in output voltage V.sub.OUT is stopped quickly and the output voltage is restored to the normal level within a short time.
摘要翻译：一种用于提供诸如电源电压VDD的1 / 2VDD的规定电压的电压产生电路，其中电压产生电路的电流和响应时间的容量显着提高。当电压产生电路的输出电压VOUT从参考值1 / 2VDD突然下降并且低于容许电压电平VM-的下限时，输出电压检测电路14的n型MOS晶体管MN5A导通。数字输出电路16中的p型MOS晶体管MP6A的栅极端子的电位经导通的晶体管MN5A被拉到输出电压VOUT的电平，并且所述p型MOS晶体管MP6A导通在饱和区域或多或少完美。由于在饱和区域中经由p型MOS晶体管MP6A从电源端子18流过至端子侧（即负载电路侧）的输出侧的大量电流，输出电压VOUT的降低快速停止，并且输出电压在短时间内恢复到正常水平。

27. 发明授权

US5528538A Voltage generating circuit in semiconductor integrated circuit 失效
标题翻译：半导体集成电路中的电压产生电路
公开(公告)号：US5528538A
公开(公告)日：1996-06-18
申请号：US84628
申请日：1993-06-30
申请人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
发明人： Toshiyuki Sakuta , Tomohiro Suzuki , Yuriko Iizuka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C7/00
CPC分类号： G11C5/145 , G11C5/143
摘要： A voltage generating circuit in a semiconductor integrated circuit driven by two sorts of power supply voltages, includes a unit for generating plural sorts of signals; a unit for selecting one of the plural sorts of signals in response to an operation mode of the semiconductor integrated circuit; and a pumping unit for producing either a first predetermined voltage higher than the high power supply voltage among the two sorts of power supply voltages, or a second predetermined voltage lower than the low power supply voltage by a pumping operation based upon the signal selected by the selecting unit.
摘要翻译：由两种电源电压驱动的半导体集成电路中的电压产生电路包括用于产生多种信号的单元; 用于响应半导体集成电路的操作模式选择多种信号之一的单元; 以及泵送单元，用于在两种电源电压之中产生高于高电源电压的第一预定电压，或者通过基于由所述电源电压选择的信号的泵送操作产生低于低电源电压的第二预定电压选择单位。

28. 发明授权

US5301142A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5301142A
公开(公告)日：1994-04-05
申请号：US895598
申请日：1992-06-08
申请人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
发明人： Yukihide Suzuki , Masaya Muranaka , Hiromi Matsuura , Yoshinobu Nakagome , Hitoshi Tanaka , Eiji Yamasaki , Toshiyuki Sakuta
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C7/10
摘要： Each of a plurality of memory arrays is divided into a plurality of memory mats MAT00L-MAT07L to MAT10R-MAT17R in directions in which word lines and bit lines extend. First common data lines, that is, sub-IO lines, are provided which correspond to these memory mats and which are disposed in parallel to the word lines. Bit lines designating the corresponding memory mats are selectively connected to the first common data lines. Second common data lines, that is, main IO line groups MIOG0-MIOG7, are also provided and are disposed in parallel to the bit lines. Designated sub-IO lines are selectively connected to the second common data lines. Moreover, a plurality of main amplifiers forming a main amplifier unit MAU0 are orderly arranged in the direction in which the bit lines extend. These include a first main amplifier comprising a static current mirror amplifier which requires a relatively large operating current and a second main amplifier comprising a dynamic CMOS latch amplifier which requires only a relatively small operating current. These main amplifiers are put to proper use in conformity with the operating mode involved. By virtue of these arrangements, the number of parallel bits in a multibit parallel test mode of a dynamic RAM becomes expandable without being restricted by the number of the sub-IO lines correspondingly provided for each memory mat.
摘要翻译：在字线和位线延伸的方向上，多个存储器阵列中的每一个被分成多个存储器块MAT00L-MAT07L到MAT10R-MAT17R。提供了与这些存储垫对应并且与字线平行设置的第一公共数据线，即子IO线。指定对应的存储器垫的位线选择性地连接到第一公共数据线。还提供第二公共数据线，即主IO线组MIOG0-MIOG7，并且与位线并行设置。指定的子IO线选择性地连接到第二公共数据线。此外，形成主放大器单元MAU0的多个主放大器在位线延伸的方向上有序排列。这些包括第一主放大器，其包括需要相对大的工作电流的静态电流镜放大器，以及包括仅需要较小工作电流的动态CMOS锁存放大器的第二主放大器。这些主放大器按照所涉及的工作模式正确使用。由于这些布置，动态RAM的多位并行测试模式中的并行比特数可以扩展，而不受对应于每个存储器垫的子IO线数的限制。

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