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21. 发明授权

US5483490A Semiconductor integrated device and wiring correction arrangement therefor 失效
标题翻译：半导体集成器件及其布线校正装置
公开(公告)号：US5483490A
公开(公告)日：1996-01-09
申请号：US159619
申请日：1993-12-01
申请人： Hidetoshi Iwai , Masamichi Ishihara , Kazuya Ito , Wataru Arakawa , Yoshinobu Nakagome
发明人： Hidetoshi Iwai , Masamichi Ishihara , Kazuya Ito , Wataru Arakawa , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/20 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： H01L21/76894 , G11C29/83 , G11C29/832 , H01L21/76888 , G11C8/16
摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.
摘要翻译：提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。由该预定布线整体形成的切割点或其一部分设置在该装置上。通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

22. 发明授权

US5289416A Semiconductor integrated device and wiring correction arrangement therefor 失效
标题翻译：半导体集成器件及其布线校正装置
公开(公告)号：US5289416A
公开(公告)日：1994-02-22
申请号：US820489
申请日：1992-01-14
申请人： Hidetoshi Iwai , Masamichi Ishihara , Kazuya Ito , Wataru Arakawa , Yoshinobu Nakagome
发明人： Hidetoshi Iwai , Masamichi Ishihara , Kazuya Ito , Wataru Arakawa , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/20 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/768 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： H01L21/76894 , G11C29/83 , G11C29/832 , H01L21/76888 , G11C8/16
摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.
摘要翻译：提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。由该预定布线整体形成的切割点或其一部分设置在该装置上。通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

23. 发明授权

US08952261B2 Interconnect-use electronic component and method for producing same 有权
标题翻译：互联电子元件及其制造方法
公开(公告)号：US08952261B2
公开(公告)日：2015-02-10
申请号：US13518145
申请日：2010-11-24
申请人： Masamichi Ishihara , Minoru Enomoto , Shigeru Nomura
发明人： Masamichi Ishihara , Minoru Enomoto , Shigeru Nomura
IPC分类号： H05K1/02 , H05K1/03 , H01L23/48 , H01L21/00 , H01L23/498 , H01L23/31 , H01L23/538 , H01L23/00
CPC分类号： H01L23/49827 , H01L23/3114 , H01L23/5389 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , Y10T156/10 , Y10T156/1052 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： The present invention enables additional processes required for forming vertical wiring and rewiring in a double face package (DFP) or a wafer level chip size package (WLCSP) to be implemented through use of a component for vertical wiring and rewiring, to thereby simplify the manufacturing process and reduce cost. An electronic component for interconnection is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and which has external electrodes connected to the circuit element via vertical interconnects and horizontal interconnects. This electronic component for interconnection is composed of a wiring substrate which includes horizontal interconnects and vertical interconnects connected to the horizontal interconnects and extending therefrom in a vertical direction; and a support plate to which the wiring substrate having the horizontal interconnects and the vertical interconnects is bonded through use of an adhesive which can be separated with water.
摘要翻译：本发明使得在双面封装（DFP）或晶片级芯片尺寸封装（WLCSP）中形成垂直布线和重新布线所需的附加工艺将通过使用用于垂直布线和重新布线的部件来实现，从而简化制造过程并降低成本。用于互连的电子部件被结合到其中设置有包括半导体芯片的电路元件并且具有通过垂直互连和水平互连连接到电路元件的外部电极的电子器件封装中。该用于互连的电子部件由布线基板构成，该布线基板包括水平互连件和连接到水平互连件的垂直互连件，并在垂直方向上从该互连件延伸; 以及支撑板，其中具有水平互连的布线基板和垂直互连件通过使用可与水分离的粘合剂粘合到该支撑板上。

24. 发明申请

US20140327024A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140327024A1
公开(公告)日：2014-11-06
申请号：US14236584
申请日：2012-07-31
申请人： Masamichi Ishihara , Kenshu Oyama , Shoji Murakami , Hitonobu Onosaka
发明人： Masamichi Ishihara , Kenshu Oyama , Shoji Murakami , Hitonobu Onosaka
IPC分类号： H01L33/60
CPC分类号： H01L33/60 , H01L24/97 , H01L25/0753 , H01L33/62 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48228 , H01L2224/73265 , H01L2224/97 , H01L2924/01029 , H01L2924/07802 , H01L2924/12041 , H01L2924/12042 , H01L2924/15747 , H01L2924/15787 , H01L2924/181 , H05K1/056 , H05K2201/0209 , H05K2201/10106 , H05K2201/2054 , H01L2224/81 , H01L2224/85 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes an electrical insulating layer with superior heat resistance, heat dissipation, and durability, and which is manufactured through a process with good cost performance and process performance. In a semiconductor device including a first substrate to which a semiconductor chip is mounted directly or indirectly, and a white insulating layer formed on a surface of the first substrate and functioning as a reflecting material, the semiconductor chip is an LED, at least the surface of the first substrate is made of a metal, and a stacked structure of the white insulating layer and a metal layer is formed by coating a liquid material, which contains SiO2 in the form of nanoparticles and a white inorganic pigment, over the surface of the first substrate and baking the coated liquid material.
摘要翻译：半导体器件包括具有优异的耐热性，散热性和耐久性的电绝缘层，并且通过具有良好的性价比和工艺性能的工艺制造。在包括直接或间接安装有半导体芯片的第一基板和形成在第一基板的表面上并用作反射材料的白色绝缘层的半导体器件中，半导体芯片至少是表面的第一衬底由金属制成，并且通过在其表面上涂覆含有纳米颗粒和白色无机颜料形式的SiO 2的液体材料来形成白色绝缘层和金属层的层叠结构第一衬底和烘烤涂覆的液体材料。

25. 发明授权

US08501542B2 Double-faced electrode package, and its manufacturing method 有权
标题翻译：双面电极封装及其制造方法
公开(公告)号：US08501542B2
公开(公告)日：2013-08-06
申请号：US13412128
申请日：2012-03-05
申请人： Masamichi Ishihara , Harufumi Kobayashi
发明人： Masamichi Ishihara , Harufumi Kobayashi
IPC分类号： H01L21/50
CPC分类号： H01L23/3107 , H01L21/4842 , H01L23/49548 , H01L23/49551 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
摘要翻译：双面包装具有用模制树脂密封的LSI芯片，以及在前表面和背面两者上的用于外部连接的电极。 LSI芯片被接合到引线框架的芯片焊盘上，引线框架的外部引线部分至少在背面被暴露为背面电极。引线框架的LSI芯片和多个内部引线部分通过布线连接。多个内部引线部分中的至少一些具有通过对引线框架的一部分进行加工而一体形成的正面电极。连接到前面电极的各个头表面的前面电极或凸起电极的头表面用作用于与另一衬底，元件等的外部连接的电极。

26. 发明申请

US20120164790A1 DOUBLE-FACED ELECTRODE PACKAGE, AND ITS MANUFACTURING METHOD 有权
标题翻译：双面电极包装及其制造方法
公开(公告)号：US20120164790A1
公开(公告)日：2012-06-28
申请号：US13412128
申请日：2012-03-05
申请人： Masamichi Ishihara , Harufumi Kobayashi
发明人： Masamichi Ishihara , Harufumi Kobayashi
IPC分类号： H01L21/78 , H01L21/60
CPC分类号： H01L23/3107 , H01L21/4842 , H01L23/49548 , H01L23/49551 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.
摘要翻译：双面包装具有用模制树脂密封的LSI芯片，以及在前表面和背面两者上的用于外部连接的电极。 LSI芯片被接合到引线框架的芯片焊盘上，引线框架的外部引线部分至少在背面被暴露为背面电极。引线框架的LSI芯片和多个内部引线部分通过布线连接。多个内部引线部分中的至少一些具有通过对引线框架的一部分进行加工而一体形成的正面电极。连接到前面电极的各个头表面的前面电极或凸起电极的头表面用作用于与另一衬底，元件等的外部连接的电极。

27. 发明授权

US07884466B2 Semiconductor device with double-sided electrode structure and its manufacturing method 有权
标题翻译：具有双面电极结构的半导体器件及其制造方法
公开(公告)号：US07884466B2
公开(公告)日：2011-02-08
申请号：US12279402
申请日：2007-04-09
申请人： Masamichi Ishihara , Fumihiko Ooka , Yoshihiko Ino
发明人： Masamichi Ishihara , Fumihiko Ooka , Yoshihiko Ino
IPC分类号： H01L23/12
CPC分类号： H01L23/13 , H01L23/49822 , H01L23/49838 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/105 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/92247 , H01L2225/1058 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15156 , H01L2924/1517 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/00014
摘要： According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring.
摘要翻译：根据本发明，在具有多层布线的多层有机基板形成的封装基板中形成有凹部，在该凹部内容纳有LSI芯片。在密封连接到多层布线的LSI芯片的树脂的上表面上形成接线迹线。布线迹线连接到连接到封装基板前表面上的多层布线的端子布线迹线和在树脂上表面上用于外部连接的前面凸块电极。在封装基板的背面侧形成有用于外部连接的背面凸块电极并连接到多层布线。

28. 发明申请

US20080265430A1 Semiconductor Device an Process for Fabricating the Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080265430A1
公开(公告)日：2008-10-30
申请号：US10577863
申请日：2005-11-21
申请人： Masamichi Ishihara
发明人： Masamichi Ishihara
IPC分类号： H01L23/52 , H01L21/00
CPC分类号： H01L23/481 , H01L23/3157 , H01L23/48 , H01L23/488 , H01L23/49838 , H01L24/13 , H01L25/04 , H01L25/0652 , H01L25/0657 , H01L29/78 , H01L2224/0554 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/13025 , H01L2224/1403 , H01L2224/16145 , H01L2224/16146 , H01L2224/16148 , H01L2224/16225 , H01L2224/17181 , H01L2224/81191 , H01L2224/81193 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/3011 , H01L2924/00 , H01L2924/013 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes.
摘要翻译：薄堆叠半导体器件具有多个电路，其以指定图案依次层叠并形成以形成多层布线部。在形成多层布线部的阶段，在半导体基板上形成填充电极，使得表面被绝缘膜覆盖，在多层布线部的特定布线上形成柱状电极，形成第一绝缘层在半导体衬底的一个表面上，将第一绝缘层的表面去除特定厚度以暴露后电极，并且研磨半导体衬底的另一个表面以露出填充电极并形成通孔型电极在半导体衬底的一个表面上形成第二绝缘层，同时露出直通型电极的前端，并且在两个电极上形成凸起电极。

29. 发明授权

US5458998A Method of making mask pattern data and process for manufacturing the mask 失效
标题翻译：制作掩模图案数据的方法和用于制造掩模的工艺
公开(公告)号：US5458998A
公开(公告)日：1995-10-17
申请号：US886403
申请日：1992-05-21
申请人： Toshitsugu Takekuma , Toshio Suzuki , Hidetoshi Iwai , Masamichi Ishihara
发明人： Toshitsugu Takekuma , Toshio Suzuki , Hidetoshi Iwai , Masamichi Ishihara
IPC分类号： G03F1/00 , G03F1/26 , G03F1/30 , G03F1/36 , G03F1/68 , G03F1/84 , H01L21/027 , H01L21/30 , G03F9/00
CPC分类号： G03F1/26 , G03F1/29 , G03F1/84
摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.
摘要翻译：可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （108）通过从被检查和校正的正确的实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。

30. 发明授权

US4802135A Semiconductor memory having multiple continuous access functions 失效
标题翻译：具有多个连续访问功能的半导体存储器
公开(公告)号：US4802135A
公开(公告)日：1989-01-31
申请号：US902564
申请日：1986-09-02
申请人： Takashi Shinoda , Masamichi Ishihara
发明人： Takashi Shinoda , Masamichi Ishihara
IPC分类号： G11C11/34 , G11C7/10 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/408 , G11C11/40 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1021 , G11C7/1027 , G11C7/1045 , G11C7/1048 , G11C8/18
摘要： A pseudo static RAM is provided which uses a one MOSFET dynamic RAM cell, in which two functions of a page mode and a static column mode are realized by using an address buffer having a function to transmit address signals fed from external terminals as they are and a latch function to latch the address signals fed from the external terminals in synchronism with predetermined control signals fed from the external terminals. The address buffer also has a multiplexer function to selectively incorporate the address signals from the external terminals and the address signals produced in the inside of the RAM so that the address buffer and an internal address signal generating circuit may be controlled by external control terminals to make possible the continuous access by the internal address signals.
摘要翻译：提供了一种伪静态RAM，其使用一个MOSFET动态RAM单元，其中通过使用具有从外部端子原样馈送的地址信号的功能的地址缓冲器来实现页面模式和静态列模式的两个功能，以及锁存功能，用于与从外部端子馈送的预定控制信号同步地锁存从外部端子馈送的地址信号。地址缓冲器还具有多路复用功能，用于选择性地并入来自外部端子的地址信号和在RAM内部产生的地址信号，使得地址缓冲器和内部地址信号发生电路可以由外部控制端子控制，可能通过内部地址信号的连续访问。

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