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21. 发明授权

US5633275A Photochemotherapeutical obstruction of newly-formed blood vessels 失效
标题翻译：新形成的血管的光化学治疗性阻塞
公开(公告)号：US5633275A
公开(公告)日：1997-05-27
申请号：US616177
申请日：1996-03-15
申请人： Keisuke Mori , Masataka Ohta , Shigeru Mori , Shin Yoneya , Naoki Hayashi , Masaru Sonoda
发明人： Keisuke Mori , Masataka Ohta , Shigeru Mori , Shin Yoneya , Naoki Hayashi , Masaru Sonoda
IPC分类号： C07D487/22 , A61K31/00 , A61K31/40 , A61K31/409 , A61K41/00 , A61P27/00 , A61P27/02 , A61P27/04 , A61P43/00
CPC分类号： A61K41/0071 , A61K31/409
摘要： A photosensitive tetrapyrrole derivative having formula (I) ##STR1## where n stands for 1 or 2 or a pharmaceutically acceptable salt thereof is useful as an effective ingredient in an obstruent composition for photochemotherapeutically obstructing neovascular vessels. The photosensitive tetrapyrroles of the formula (I) may be administered in a photochemotherapeutic method for obstructing neovascular vessels, particularly choroidal and retinal neovascularizations.
摘要翻译：具有式（I）的光敏四吡咯衍生物（I）其中n代表1或2或其药学上可接受的盐可用作用于光化学治疗性阻塞新生血管血管的组合物中的有效成分。式（I）的光敏四吡咯可以以光化学治疗方法施用，用于阻塞新血管血管，特别是脉络膜和视网膜新血管形成。

22. 发明授权

US5600281A Oscillator circuit generating a clock signal having a temperature dependent cycle and a semiconductor memory device including the same 失效
标题翻译：产生具有温度相关周期的时钟信号的振荡器电路和包括该时钟信号的半导体存储器件
公开(公告)号：US5600281A
公开(公告)日：1997-02-04
申请号：US577354
申请日：1995-12-22
申请人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
发明人： Shigeru Mori , Takeshi Kajimoto , Masanori Hayashikoshi
IPC分类号： G11C11/406 , G11C11/4076 , H03K3/03 , H03K3/354 , G01K7/00 , H03B5/02
CPC分类号： G11C11/4076 , G11C11/406 , H03K3/0315 , H03K3/354
摘要： In a semiconductor memory device, a constant voltage is applied to a resistor having a positive temperature coefficient, whereby a first reference current flowing through that resistor is converted into a voltage by a resistor. That voltage is converted into a second reference current by a P channel MOS transistor, whereby a second current of a value equal to the value of the second reference current flows through each of a plurality of inverters by a current mirror circuit. These inverters are connected in a ring manner to form a ring oscillator. The first reference current becomes lower as the operating temperature rises, whereby the second reference current increases. As a result, the oscillator cycle of the ring oscillator becomes shorter as the operating temperature rises.
摘要翻译：在半导体存储器件中，将恒定电压施加到具有正温度系数的电阻器，由此流过该电阻器的第一参考电流被电阻器转换成电压。该电压通过P沟道MOS晶体管转换为第二基准电流，由此通过电流镜电路使等于第二基准电流的值的第二电流流过多个反相器中的每一个。这些反相器以环形方式连接以形成环形振荡器。随着工作温度升高，第一参考电流变低，从而第二参考电流增加。结果，环路振荡器的振荡器周期随着工作温度升高而变短。

23. 发明授权

US5587648A Power supply circuit for generating an internal power supply potential based on an external potential 失效
标题翻译：用于基于外部电位产生内部电源电位的电源电路
公开(公告)号：US5587648A
公开(公告)日：1996-12-24
申请号：US378217
申请日：1995-01-25
申请人： Shinichi Jinbo , Shigeru Mori
发明人： Shinichi Jinbo , Shigeru Mori
IPC分类号： G11C11/407 , G11C5/14 , G11C11/409 , G05F1/613
CPC分类号： G11C5/147 , G11C5/14
摘要： An internal power supply circuit of the present invention includes a primary internal power supply potential supplying circuit, two auxiliary internal power supply potential supplying circuits, and a P channel MOS transistor. The internal power supply potential supplying circuit always supplies an internal power supply potential to a first output node based on an external power supply potential. One auxiliary internal power supply potential supplying circuit is activated in response to a control signal, and, when activated, supplies the internal power supply potential to the first output node. The other auxiliary internal power supply potential supplying circuit is activated in response to another control signal, and, when activated, supplies the internal power supply potential to a second output node. The P channel MOS transistor is connected between the first output node and the second output node. The P channel MOS transistor has a gate electrode receiving the control signal.
摘要翻译：本发明的内部电源电路包括主内部电源电位供给电路，两个辅助内部电源电位供给电路和P沟道MOS晶体管。内部电源电位供应电路总是基于外部电源电位向第一输出节点提供内部电源电位。响应于控制信号激活一个辅助内部电源电位供应电路，并且当被激活时，将内部电源电位提供给第一输出节点。另一个辅助内部电源电位供应电路响应于另一个控制信号被激活，并且当被激活时，将内部电源电位提供给第二输出节点。 P沟道MOS晶体管连接在第一输出节点和第二输出节点之间。 P沟道MOS晶体管具有接收控制信号的栅电极。

24. 发明授权

US5566517A Architectural panel 失效
标题翻译：建筑面板
公开(公告)号：US5566517A
公开(公告)日：1996-10-22
申请号：US364475
申请日：1994-12-27
申请人： Mikio Ishii , Shigeru Mori
发明人： Mikio Ishii , Shigeru Mori
IPC分类号： E04F13/24 , E04C2/52 , E04F13/08 , E04F13/21 , E04H17/14 , E04B2/00
CPC分类号： E04C2/526 , E04F13/0862
摘要： A projection is formed on the back of the bed of an architectural panel used as a fence, a gate or a wall of a building, and a groove is formed in the same direction as the projection. The projection of one face member is fitted in the groove of another face member which makes a pair with the former face member. This prevents the projection from being broken during transportation or the like.
摘要翻译：在用作建筑物的围栏，门或墙的建筑板的床的后部形成突起，并且在与突起相同的方向上形成槽。一个面部构件的突起装配在与前面部构件成对的另一个面部构件的凹槽中。这防止了在运输等期间突起被破坏。

25. 发明授权

US5532961A Semiconductor memory device having extended data out function 失效
标题翻译：具有扩展数据输出功能的半导体存储器件
公开(公告)号：US5532961A
公开(公告)日：1996-07-02
申请号：US345758
申请日：1994-11-22
申请人： Shigeru Mori , Tomio Suzuki , Masanori Hayashikoshi
发明人： Shigeru Mori , Tomio Suzuki , Masanori Hayashikoshi
IPC分类号： G11C11/417 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409 , G11C11/4093 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/4093 , G11C11/4096 , G11C7/1024 , G11C7/1051 , G11C7/106
摘要： A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.
摘要翻译： DRAM包括输出端子，具有多个存储单元的存储单元阵列，行解码器，列解码器，输入/输出电路，数据扩展电路，输出缓冲电路和控制电路。数据扩展电路扩展从输入/输出电路读出的每个数据，直到读出后续数据。输出缓冲器电路响应来自数据扩展电路的扩展数据，以将输出数据顺序地提供给输出端。响应于从控制电路提供的输出控制信号，在从输出缓冲器电路提供每个输出数据之前，将输出端子设置为高阻抗状态。

26. 发明授权

US5519650A Semiconductor device having an improved immunity to a short-circuit at a power supply line 失效
标题翻译：具有对电源线短路的抗干扰性的半导体装置
公开(公告)号：US5519650A
公开(公告)日：1996-05-21
申请号：US301752
申请日：1994-09-07
申请人： Tooru Ichimura , Kazuhiro Sakemi , Shigeru Mori , Mikio Sakurai
发明人： Tooru Ichimura , Kazuhiro Sakemi , Shigeru Mori , Mikio Sakurai
IPC分类号： G11C11/41 , G11C29/50 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L23/525 , G11C5/06
CPC分类号： G11C29/50 , H01L23/5258 , H01L2924/0002
摘要： A semiconductor memory device includes a memory cell array (1) having a plurality of memory cells arranged in rows and columns, a plurality of column select lines (3) extending over the memory cell array and coupled to received column select signals generated by a column decoder (100), a plurality of power supply lines (4) provided in parallel with the column select lines to transfer a power supply voltage from a main power supply line (130), and a plurality of ground lines (5) provided in parallel with the column select lines to transfer a ground voltage from a main ground line. A plurality of fuse elements (6) are provided for each of the column select lines. When a short-circuit is found between a column select line and power supply line or a ground line, a fuse element corresponding to the short-circuited column select line is blown off and the short-circuited column select line is isolated from the column decoder. By repairing the short-circuited column select line with a redundant column select line (60), the memory device operates correctly without an adverse effect of the short-circuit.
摘要翻译：半导体存储器件包括具有以行和列排列的多个存储器单元的存储单元阵列（1），在存储单元阵列上延伸的多个列选择线（3），并与由列产生的接收列选择信号耦合解码器（100），与列选择线并联设置的多个电源线（4），用于传送来自主电源线（130）的电源电压和并联设置的多个接地线（5）列选择线从主地线传输接地电压。为每个列选择线提供多个熔丝元件（6）。当在列选择线和电源线或接地线之间发现短路时，与短路列选择线相对应的熔丝元件被断开，并且短路列选择线与列解码器隔离。通过修复具有冗余列选择线（60）的短路列选择线，存储器件正常工作而没有短路的不利影响。

27. 发明授权

US5451896A Semiconductor integrated circuit device with an internal voltage-down converter 失效
标题翻译：具有内部降压转换器的半导体集成电路器件
公开(公告)号：US5451896A
公开(公告)日：1995-09-19
申请号：US980414
申请日：1992-11-20
申请人： Shigeru Mori
发明人： Shigeru Mori
IPC分类号： G11C11/407 , G11C11/401 , G11C29/00 , G11C29/06 , H01L27/02 , G05F1/10
CPC分类号： H01L27/0214
摘要： A semiconductor integrated circuit device includes an aging mode control circuit, which detects the times of toggle of an external supply voltage (external Vcc) with a predetermined amplitude and generates an aging mode enable signal, and an internal voltage reduction circuit transmitting a voltage, which changes in accordance with change of the external supply voltage (external Vcc), onto an internal supply line in response to the aging mode enable signal. The semiconductor integrated circuit device enters an aging mode only when the external supply voltage oscillates a predetermined number of times with an amplitude not less than the predetermined amplitude. The semiconductor integrated circuit device does not unnecessarily enter the aging mode for an aging test, and facilely and surely enters the aging mode without utilizing a special timing relationship of external control signals.
摘要翻译：半导体集成电路装置包括老化模式控制电路，其检测具有预定振幅的外部电源电压（外部Vcc）的触发次数并产生老化模式使能信号，以及内部电压降低电路，其传输电压，根据老化模式使能信号，根据外部电源电压（外部Vcc）的变化，改变内部电源线。仅当外部电源电压以不小于预定幅度的振幅振荡预定次数时，半导体集成电路器件进入老化模式。半导体集成电路器件不会不必要地进入用于老化测试的老化模式，并且在不利用外部控制信号的特殊定时关系的情况下，便利且可靠地进入老化模式。

28. 发明授权

US5384382A Crosslinkable polysilane compositions and cured products thereof 失效
标题翻译：可交联聚硅烷组合物及其固化产物
公开(公告)号：US5384382A
公开(公告)日：1995-01-24
申请号：US96273
申请日：1993-07-26
申请人： Shigeru Mori , Eiichi Tabei , Hisashi Umehara
发明人： Shigeru Mori , Eiichi Tabei , Hisashi Umehara
IPC分类号： C08L83/14 , C08G77/08
CPC分类号： C08L83/14
摘要： Crosslinkable polysilane compositions contain (1) an alkenylsiloxy--terminated polysilane and a compound having at least three hydrosilyl groups in a molecule, (2) a hydro--siloxy--terminated polysilane and a compound having at least three alkenyl groups in a molecule, (3) a hydro--terminated polysilane and a compound having at least three alkenyl groups in a molecule, or (4) an alkenyl--terminated polysilane and a compound having at least three hydrosilyl groups in a molecule. By effecting hydrosilylation reaction between the components in the presence of a hydrosilylation catalyst, a tough crosslinked film is obtained without causing scission of a polysilane chain.
摘要翻译：可交联聚硅烷组合物含有（1）分子内具有至少三个氢化甲硅烷基的烯基甲硅烷氧基封端的聚硅烷和具有至少三个氢化甲硅烷基的化合物，（2）分子中具有至少三个烯基的水 - 甲硅烷氧基封端的聚硅烷和（3））加氢封端的聚硅烷和分子中具有至少三个烯基的化合物，或（4）分子内具有至少三个氢化甲硅烷基的烯基封端的聚硅烷和化合物。通过在氢化硅烷化催化剂的存在下进行组分之间的氢化硅烷化反应，获得坚韧的交联膜而不引起聚硅烷链断裂。

29. 发明授权

US5323349A Dynamic semiconductor memory device having separate read and write data bases 失效
标题翻译：具有分离的读和写数据库的动态半导体存储器件
公开(公告)号：US5323349A
公开(公告)日：1994-06-21
申请号：US936454
申请日：1992-08-28
申请人： Kei Hamade , Shigeru Mori
发明人： Kei Hamade , Shigeru Mori
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/4096 , G11C11/416 , H01L21/8242 , H01L27/108 , G11C7/00 , G11C11/40
CPC分类号： G11C7/1048 , G11C11/4096
摘要： Separated IO type dynamic memory device includes a write data bus for transmitting data to be written into a selected memory cell and a read data bus for transferring data read out from a selected memory cell. The write data bus and the read data bus are separately provided from each other. The memory device further includes a load circuit for supplying a current flow to the read data bus and for precharging the read data bus to a predetermined potential, and drive circuits provided for each pair of bit lines each connecting memory cells of a column for driving the read data bus to a potential corresponding to potentials appearing on an associated pair of bit lines in response to a column select signal. The memory device further includes an insulated gate type transistor inserted on the read data bus between the loading circuit and the driving circuits and receives a predetermined intermediate potential at the gate. An output node for supplying an output data is provided between the insulated gate type transistor and the load circuit. This enables fast discharging of the read data bus at the output node, resulting in a high speed data reading operation.
摘要翻译：分离式IO型动态存储装置包括用于发送要写入所选存储单元的数据的写数据总线和用于传送从所选存储单元读出的数据的读数据总线。写数据总线和读数据总线彼此分开设置。存储装置还包括用于将电流提供给读数据总线并用于将读数据总线预充电到预定电位的负载电路，以及为每对连接列驱动的列的存储单元而设置的驱动电路响应于列选择信号将数据总线读取到对应于出现在相关联的位线对上的电位的电位。存储器件还包括插入在读取数据总线上的负载电路和驱动电路之间的绝缘栅型晶体管，并在栅极处接收预定的中间电位。在绝缘栅型晶体管和负载电路之间设置用于提供输出数据的输出节点。这使得能够在输出节点处读取数据总线的快速放电，导致高速数据读取操作。

30. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

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