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    • 21. 发明授权
    • Deposition film orientation and reflectivity improvement using a
self-aligning ultra-thin layer
    • 使用自对准超薄层的沉积膜取向和反射率提高
    • US6120844A
    • 2000-09-19
    • US622941
    • 1996-03-27
    • Liang ChenTed GuoFusen ChenRoderick C. Mosely
    • Liang ChenTed GuoFusen ChenRoderick C. Mosely
    • H01L21/28C23C14/56C23C16/54H01L21/02H01L21/203H01L21/285H01L21/3205H01L21/677H01L21/768C23C14/34C23C16/06C23C16/22
    • H01L21/76876C23C14/568C23C16/54H01L21/32051H01L21/76843H01L21/76877H01L21/76879
    • The present invention relates generally to an improved apparatus and process to provide a thin self-aligning layer prior to forming a conducting film layer thereover to improve the film characteristics and deposition coverage. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by either vapor deposition or chemical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. In another aspect of the invention, a thin, self-aligning layer is formed over a barrier layer prior to deposition of a conducting film thereover. It is believed that the self-aligning layer enhances the reflectivity of the films by improving the crystal structure in the resulting film and provides improved electromigration performance by providing crystal orientation. The process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the process occurs without the formation of oxides between the layers.
    • 本发明一般涉及在形成导电膜层之前提供薄的自对准层以改善膜特性和沉积覆盖的改进的装置和工艺。 在本发明的一个方面,电介质层形成在导电或半导体层之上,并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过气相沉积或化学气相沉积将超薄成核层沉积到电介质层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积,同时优选地还在场上形成高度取向的覆盖层。 在本发明的另一方面,在其上沉积导电膜之前,在阻挡层上方形成薄的自对准层。 据认为,通过改善所得膜中的晶体结构,自对准层增强了膜的反射率,并通过提供<111>晶体取向来提供改善的电迁移性能。 该方法优选在包括PVD和CVD处理室的集成处理系统中进行,使得一旦将基底引入真空环境中,则该过程发生而不在层之间形成氧化物。
    • 22. 发明授权
    • Blanket-selective chemical vapor deposition using an ultra-thin
nucleation layer
    • 使用超薄成核层的毯选择性化学气相沉积
    • US6066358A
    • 2000-05-23
    • US611108
    • 1996-03-05
    • Ted GuoLiang ChenFusen ChenRoderick C. Mosely
    • Ted GuoLiang ChenFusen ChenRoderick C. Mosely
    • H01L21/285C23C14/56C23C16/54H01L21/28H01L21/3205H01L21/677H01L21/768B05D5/12C23C14/04C23C16/04C23C16/06
    • H01L21/76876C23C14/568C23C16/54H01L21/32051H01L21/76843H01L21/76877H01L21/76879
    • The present invention relates generally to an improved apparatus and process for providing uniform step coverage on a substrate and planarization of conducting layers to form continuous, void-free interconnects in sub-half micron, high aspect ratio aperture width applications and highly oriented conducting layers. In one aspect of the invention, a dielectric layer is formed over a conducting or semiconducting layer and etched to form an aperture exposing the underlying conducting or semiconducting layer on the aperture floor. An ultra-thin nucleation layer is then deposited by physical vapor deposition onto the field of the dielectric layer. A CVD metal layer is then deposited onto the structure to achieve selective deposition on the floor of the aperture, while preferably also forming a highly oriented blanket layer on the field. The present apparatus and process reduce the number of steps necessary to fabricate CVD metal interconnects and layers that are substantially void-free and planarized. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the apertures to form vias and contacts occurs without the formation of oxides between the layers.
    • 本发明一般涉及一种改进的装置和方法,用于在衬底上提供均匀的台阶覆盖和导电层的平坦化,以形成半微米,高纵横比孔径宽度应用和高度取向导电层的连续的无空隙互连。 在本发明的一个方面,电介质层形成在导电或半导体层之上,并被蚀刻以形成露出孔底板上下面的导电或半导体层的孔。 然后通过物理气相沉积将超薄成核层沉积到介电层的场上。 然后将CVD金属层沉积到结构上以实现孔的地板上的选择性沉积,同时优选地还在场上形成高度取向的覆盖层。 本装置和工艺减少了制造基本上无空隙和平坦化的CVD金属互连和层所需的步骤数量。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行,使得一旦将衬底引入真空环境中,孔的金属化形成通孔和接触,而不会在两者之间形成氧化物之间 层。
    • 24. 发明申请
    • Multi-track magnetron exhibiting more uniform deposition and reduced rotational asymmetry
    • 多轨磁控管具有更均匀的沉积和减小的旋转不对称性
    • US20060144703A1
    • 2006-07-06
    • US11029641
    • 2005-01-05
    • Hong YangTza-Jing GungJian-Xin LeiTed Guo
    • Hong YangTza-Jing GungJian-Xin LeiTed Guo
    • C23C14/00
    • H01J37/3408H01J37/3405
    • A multi-track magnetron having a convolute shape and asymmetric about the target center about which it rotates. A plasma track is formed as a closed loop between opposed inner and outer magnetic poles, preferably as two or three radially arranged and spirally shaped counter-propagating tracks with respect to the target center and preferably passing over the rotation axis. The pole shape may be optimized to produce a cumulative track length distribution conforming to the function L=arn. After several iterations of computerized optimization, the pole shape may be tested for sputtering uniformity with different distributions of magnets in the fabricated pole pieces. If the uniformity remains unsatisfactory, the design iteration is repeated with a different n value, different number of tracks, or different pole widths. The optimization reduces azimuthal sidewall asymmetry and improves radial deposition uniformity.
    • 具有卷绕形状且围绕其旋转的目标中心不对称的多轨磁控管。 等离子体轨道形成为相对的内部和外部磁极之间的闭合回路,优选地相对于目标中心并且优选地通过旋转轴线而形成为两个或三个径向布置且螺旋形的反向传播轨迹。 极点形状可以被优化以产生符合函数L = ar 的累积轨迹长度分布。 经过数次迭代的计算机化优化,可以测试极点形状,使其在制造的极片中具有不同的磁体分布的溅射均匀性。 如果均匀性不能令人满意,则使用不同的n值,不同数量的轨道或不同的极宽重复设计迭代。 优化可减少方位角侧壁不对称性,提高径向沉积均匀性。
    • 27. 发明授权
    • Aluminum sputtering while biasing wafer
    • 铝溅射同时偏置晶圆
    • US07378002B2
    • 2008-05-27
    • US11209328
    • 2005-08-23
    • Wei Ti LeeTed GuoSang-Ho Yu
    • Wei Ti LeeTed GuoSang-Ho Yu
    • C23C14/35H01L21/44
    • C23C14/185C23C14/025C23C14/046C23C14/345
    • An aluminum sputtering process including RF biasing the wafer and a two-step aluminum fill process and apparatus used therefor to fill aluminum into a narrow via hole by sputtering under two distinctly different conditions, preferably in two different plasma sputter reactors. The first step includes sputtering a high fraction of ionized aluminum atoms onto a relatively cold wafer, e.g., held at less than 150° C., and relatively highly biased to attract aluminum atoms into the narrow holes and etch overhangs. The second step includes more neutral sputtering onto a relatively warm wafer, e.g. held at greater than 250° C., and substantially unbiased to provide a more isotropic and uniform aluminum flux. The magnetron scanned about the back of the aluminum target may be relatively small and unbalanced in the first step and relatively large and balanced in the second.
    • 一种铝溅射工艺,包括RF偏置晶片和两步铝填充工艺和装置,用于在两个明显不同的条件下,优选在两个不同的等离子体溅射反应器中通过溅射将铝填充到窄通孔中。 第一步包括将大部分电离铝原子溅射到相对冷的晶片上,例如保持在小于150℃,并且相当高的偏压以将铝原子吸引到窄孔中并蚀刻突出端。 第二步包括在相对温暖的晶片上的更中性的溅射,例如 保持在大于250℃,并且基本上无偏差以提供更多的各向同性和均匀的铝通量。 围绕铝靶的背面扫描的磁控管可能在第一步骤中相对较小并且不平衡,而在第二步中相对较大且平衡。