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21. 发明授权

US06509241B2 Process for fabricating an MOS device having highly-localized halo regions 失效
公开(公告)号：US06509241B2
公开(公告)日：2003-01-21
申请号：US09734754
申请日：2000-12-12
申请人： Heemyong Park , Anda C. Mocuta , Paul A. Ronsheim
发明人： Heemyong Park , Anda C. Mocuta , Paul A. Ronsheim
IPC分类号： H01L21336
CPC分类号： H01L29/66636 , H01L21/26506 , H01L21/26513 , H01L21/84 , H01L27/1203 , H01L29/1045 , H01L29/1083 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66772 , H01L29/78621 , H01L29/78684
摘要： A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

22. 发明授权

US08106462B2 Balancing NFET and PFET performance using straining layers 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US08106462B2
公开(公告)日：2012-01-31
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

23. 发明申请

US20110307846A1 METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
标题翻译：参数化分析与管理方法与系统
公开(公告)号：US20110307846A1
公开(公告)日：2011-12-15
申请号：US13216362
申请日：2011-08-24
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

24. 发明授权

US08042070B2 Methods and system for analysis and management of parametric yield 有权
标题翻译：参数收益分析与管理方法与系统
公开(公告)号：US08042070B2
公开(公告)日：2011-10-18
申请号：US11876853
申请日：2007-10-23
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

25. 发明申请

US20110082680A1 COMPACT MODEL FOR DEVICE/CIRCUIT/CHIP LEAKAGE CURRENT (IDDQ) CALCULATION INCLUDING PROCESS INDUCED UPLIFT FACTORS 失效
标题翻译：用于器件/电路/芯片泄漏电流（IDDQ）的紧凑型模型包括工艺引起的升级因素
公开(公告)号：US20110082680A1
公开(公告)日：2011-04-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50 , G06F17/18 , G01R31/26
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

26. 发明申请

US20090179269A1 Protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中防止充电损坏
公开(公告)号：US20090179269A1
公开(公告)日：2009-07-16
申请号：US12317310
申请日：2008-12-22
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.
摘要翻译：芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。或者，体器件可以包括NFET，并且SOI器件可以包括PFET。当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

27. 发明授权

US07560326B2 Silicon/silcion germaninum/silicon body device with embedded carbon dopant 失效
标题翻译：硅/硅锗/硅体器件与嵌入式碳掺杂剂
公开(公告)号：US07560326B2
公开(公告)日：2009-07-14
申请号：US11381810
申请日：2006-05-05
申请人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
发明人： Anda C. Mocuta , Dureseti Chidambarrao , Ricardo A. Donaton , David M. Onsongo , Kern Rim
IPC分类号： H01L21/8234 , H01L31/0392
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/66636 , H01L29/78687
摘要： A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.
摘要翻译：一种制造半导体器件的半导体结构和方法，特别是NFET器件。这些装置包括在应力诱导层上提供的应力接收层，其中在其间的界面处的材料减少了结构中失配位错的发生和传播。应力接收层是硅（Si），应力诱导层是硅锗（SiGe），并且材料是在形成器件期间通过掺杂层提供的碳。也可以在整个SiGe层中掺杂碳。

28. 发明申请

US20090106714A1 METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
标题翻译：参数化分析与管理方法与系统
公开(公告)号：US20090106714A1
公开(公告)日：2009-04-23
申请号：US11876853
申请日：2007-10-23
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F9/45
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

29. 发明申请

US20080179680A1 PSEUDOMORPHIC SI/SIGE/SI BODY DEVICE WITH EMBEDDED SIGE SOURCE/DRAIN 失效
标题翻译： PSEUDOMORPHIC SI / SIGE / SI身体装置与嵌入式信号源/排水
公开(公告)号：US20080179680A1
公开(公告)日：2008-07-31
申请号：US12054812
申请日：2008-03-25
申请人： Dureseti CHIDAMBARRAO , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti CHIDAMBARRAO , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

30. 发明授权

US07067400B2 Method for preventing sidewall consumption during oxidation of SGOI islands 失效
标题翻译：防止SGOI岛氧化期间侧壁消耗的方法
公开(公告)号：US07067400B2
公开(公告)日：2006-06-27
申请号：US10943354
申请日：2004-09-17
申请人： Stephen W. Bedell , Anda C. Mocuta
发明人： Stephen W. Bedell , Anda C. Mocuta
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/32105 , H01L21/84 , Y10S438/967
摘要： A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.
摘要翻译：提供了一种形成基本上松弛的绝缘体上硅衬底的方法，其中基本上防止或消除了在高温松弛退火期间消耗含SiGe的岛结构的侧壁。该方法用于保持图案化含SiGe岛的原始横向尺寸，同时提供独立于每个岛尺寸的岛的均匀且均匀的Ge部分。该方法包括在至少位于阻挡层上的含SiGe的岛状结构的侧壁上形成氧化掩模，所述阻挡层具有抵抗Ge扩散的作用。然后采用加热步骤在含SiGe的岛结构内引起至少松弛。氧化掩模的存在基本上防止在加热步骤期间消耗至少含SiGe的岛结构的侧壁。

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