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    • 25. 发明授权
      US4649470A Data processing system 失效
    • Data processing system
    • 数据处理系统
    • US4649470A
    • 1987-03-10
    • US435385
    • 1982-10-20
    • David H. Bernstein , Edward M. Buckley , Roger W. March , Ronald I. Gusowski, deceased
    • David H. Bernstein , Edward M. Buckley , Roger W. March , Ronald I. Gusowski, deceased
    • G06F9/26 , G06F13/36 , G06F13/42 , H03K23/66 , G06F13/38
    • H03K23/667 , G06F13/36 , G06F13/4217 , G06F9/26
    • A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations. Unique bus protocol signals are generated to prevent simultaneous access to the system bus by two competing system components and to permit substantially immediate control of the systems bus by a component without requiring a CPU decision thereon. Further, a unique system I/O interface unit permits access to certain I/O components via other I/O buses, such unit utilizing a unique polling technique to identify on an updated basis, all components present on one of such other buses. The system I/O interface unit also includes a unique frequency synthesizer unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency.
    • 一种使用微代码架构的数据处理系统，其中两级微代码系统包括垂直微控制器存储器中的一个或多个第一或“水平”微指令以及多个第二或“垂直”微指令部分。 在优选实施例中，垂直微指令部分包括一个或多个“修改器”字段，用于选择水平微指令的选择字段和用于选择其序列的下一垂直微指令部分的测序字段，水平微指令的一个或多个字段为 能够通过垂直修改器字段进行修改，以便形成用于执行数据处理操作的输出微指令。 产生独特的总线协议信号以防止由两个竞争的系统组件同时访问系统总线，并允许由组件基本上立即控制系统总线，而不需要CPU决定。 此外，独特的系统I / O接口单元允许通过其他I / O总线访问某些I / O组件，这种单元利用独特的轮询技术，以更新的方式识别存在于其中一个其它总线上的所有组件。 系统I / O接口单元还包括唯一的频率合成器单元，用于提供至少一个具有基本上恒定频率的时钟信号，该时钟信号可以响应于具有不同频率的多个输入时钟信号中的任何一个而产生。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 26. 发明授权
      US4014006A Data processing system having a unique CPU and memory tuning relationship and data path configuration 失效
    • Data processing system having a unique CPU and memory tuning relationship and data path configuration
    • 具有独特CPU和内存调谐关系和数据路径配置的数据处理系统
    • US4014006A
    • 1977-03-22
    • US646351
    • 1976-01-02
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • Karsten Sorensen , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F13/42 , G06F13/00
    • G06F13/4243 , G06F1/04 , G06F9/226
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an output and an A-input and a B-input.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 27. 发明申请
      US20130002363A1 OUT-OF-PLANE RESONATOR 有权
    • OUT-OF-PLANE RESONATOR
    • 超平面谐振器
    • US20130002363A1
    • 2013-01-03
    • US13173449
    • 2011-06-30
    • Mehrnaz Motiee , Emmanuel P. Quevy , David H. Bernstein
    • Mehrnaz Motiee , Emmanuel P. Quevy , David H. Bernstein
    • H03B5/30
    • H03H9/2457 , H03H9/2452 , H03H2009/02299 , H03H2009/02511
    • A microelectromechanical system (MEMS) device includes a resonator anchored to a substrate. The resonator includes a first strain gradient statically deflecting a released portion of the resonator in an out-of-plane direction with respect to the substrate. The resonator includes a first electrode anchored to the substrate. The first electrode includes a second strain gradient of a released portion of the first electrode. The first electrode is configured to electrostatically drive the resonator in a first mode that varies a relative amount of displacement between the resonator and the first electrode. The resonator may include a resonator anchor anchored to the substrate. The first electrode may include an electrode anchor anchored to the substrate in close proximity to the resonator anchor. The electrode anchor may be positioned relative to the resonator anchor to substantially decouple dynamic displacements of the resonator relative to the electrode from changes to the substrate.
    • 微机电系统（MEMS）装置包括锚定到基板的谐振器。 谐振器包括使第一应变梯度在相对于衬底的平面外方向上静态偏转谐振器的释放部分。 谐振器包括锚定到基板的第一电极。 第一电极包括第一电极的释放部分的第二应变梯度。 第一电极被配置为以改变谐振器和第一电极之间的相对的位移量的第一模式静电驱动谐振器。 谐振器可以包括锚定到衬底的谐振器锚。 第一电极可以包括锚固到靠近谐振器锚的衬底的电极锚。 电极锚定件可以相对于谐振器锚固件定位，以基本上使谐振器相对于电极的动态位移与基板的变化相分离。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 29. 发明授权
      US4079454A Data processing system using read-only-memory arrays to provide operation in a plurality of operating states 失效
    • Data processing system using read-only-memory arrays to provide operation in a plurality of operating states
    • 数据处理系统使用只读存储器阵列来提供多个操作状态的操作
    • US4079454A
    • 1978-03-14
    • US737417
    • 1976-11-01
    • Karsten Sorenson , David H. Bernstein , Michael B. Druke
    • Karsten Sorenson , David H. Bernstein , Michael B. Druke
    • G06F1/04 , G06F9/22 , G06F13/18 , G06F13/42 , G06F13/00
    • G06F1/04 , G06F13/18 , G06F13/4243 , G06F9/226
    • A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.The logic for providing operation in a program or a non-program operating state is arranged to utilize one or more relatively small read-only-memory units for each of a plurality of selected groups of program and non-program operating states, each group using only one or two of such read-only-memory units for such purpose.The central processor unit further includes a unique arrangement interconnecting a skew protected, tri-state register file having two read and two write ports with an arithmetic logic unit having an input and an A-input and a B-input.
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