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21. 发明申请

US20120139061A1 Self-Aligned Contact For Replacement Gate Devices 有权
标题翻译：用于替代门装置的自对准触点
公开(公告)号：US20120139061A1
公开(公告)日：2012-06-07
申请号：US12958607
申请日：2010-12-02
申请人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
发明人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.
摘要翻译：替代栅极堆叠的导电顶表面通过至少一个蚀刻相对于平坦化介电层的顶表面凹陷。介电覆盖层沉积在平坦化电介质层和替代栅极堆叠的顶表面上，使得替代栅极堆叠上的介电顶盖层的一部分的顶表面相对于上述电介质层的另一部分垂直凹陷平坦化介电层。电介质覆盖层的垂直偏移可以与选择性通孔蚀刻工艺结合使用以形成自对准接触结构。

22. 发明授权

US07943457B2 Dual metal and dual dielectric integration for metal high-k FETs 有权
标题翻译：金属高k FET的双金属和双电介质集成
公开(公告)号：US07943457B2
公开(公告)日：2011-05-17
申请号：US12423236
申请日：2009-04-14
申请人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
发明人： Michael P. Chudzik , Wiliam K. Henson , Rashmi Jha , Yue Liang , Ravikumar Ramachandran , Richard S. Wise
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28185 , H01L21/823842 , H01L21/823857 , H01L29/49 , H01L29/7833
摘要： The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.
摘要翻译：在一个实施例中，本发明提供一种形成半导体器件的方法，该半导体器件包括提供包括第一导电类型区域和第二导电类型区域的衬底; 在所述基板的第一导电类型区域和所述第二导电类型区域之上形成包括栅极电介质的栅极堆叠和覆盖所述高k栅极电介质的第一金属栅极导体; 去除存在于第一导电类型区域中的第一金属栅极导体的一部分以暴露存在于第一导电类型区域中的栅极电介质; 将氮基等离子体施加到所述基板，其中所述氮基等离子体氮化存在于所述第一导电类型区域中的所述栅极电介质，并且氮化所述第二导电类型区域中存在的所述第一金属栅极导体; 以及形成覆盖存在于第一导电类型区域中的至少栅极电介质的第二金属栅极导体。

23. 发明授权

US07335969B2 Method of monitoring introduction of interfacial species 失效
标题翻译：监测界面物种引进方法
公开(公告)号：US07335969B2
公开(公告)日：2008-02-26
申请号：US11076371
申请日：2005-03-09
申请人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
发明人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
IPC分类号： H01L21/66
CPC分类号： H01L21/67167 , H01L21/02329 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/3144 , H01L21/3185 , H01L21/67213 , H01L21/67253 , H01L29/513 , H01L29/518 , Y10T29/41
摘要： A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.
摘要翻译：一种用于监测氮化工艺的方法，包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成第一电介质层; （c）将一定量的界面物质引入底物; （d）去除第一电介质层; （e）在所述衬底的顶表面上形成第二电介质层; （f）测量衬底和第二介电层之间的界面陷阱的密度; （g）提供界面物质的量与界面捕集阱的密度之间的预定关系; 和（h）基于关系确定引入的界面物质的数量。

24. 发明授权

US06929964B2 Method of monitoring introduction on interfacial species 失效
标题翻译：监测界面种类介绍的方法
公开(公告)号：US06929964B2
公开(公告)日：2005-08-16
申请号：US10605244
申请日：2003-09-17
申请人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
发明人： Lance Genicola , Mark J. Hurley , Jeremy J. Kempisty , Paul D. Kirsch , Ravikumar Ramachandran , Suri Hedge
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L21/66
CPC分类号： H01L21/67167 , H01L21/02329 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/2822 , H01L21/28238 , H01L21/3144 , H01L21/3185 , H01L21/67213 , H01L21/67253 , H01L29/513 , H01L29/518 , Y10T29/41
摘要： A method for monitoring a nitridation process, including: (a) providing a semiconductor substrate; (b) forming a first dielectric layer on a top surface of the substrate; (c) introducing a quantity of interfacial species into the substrate; (d) removing the first dielectric layer; (e) forming a second dielectric layer on the top surface of the substrate; (f) measuring the density of interface traps between the substrate and the second dielectric layer; (g) providing a predetermined relationship between the quantity of the interfacial species and the density of the interface traps; and (h) determining the quantity of the interfacial species introduced based on the relationship.
摘要翻译：一种用于监测氮化工艺的方法，包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成第一电介质层; （c）将一定量的界面物质引入底物; （d）去除第一电介质层; （e）在所述衬底的顶表面上形成第二电介质层; （f）测量衬底和第二介电层之间的界面陷阱的密度; （g）提供界面物质的量与界面捕集阱的密度之间的预定关系; 和（h）基于关系确定引入的界面物质的数量。

25. 发明申请

US20050112904A1 Clean chemistry for tungsten/tungsten nitride gates 审中-公开
标题翻译：钨/氮化钨门的清洁化学
公开(公告)号：US20050112904A1
公开(公告)日：2005-05-26
申请号：US10718381
申请日：2003-11-20
申请人： Herve Kermel , Ravikumar Ramachandran
发明人： Herve Kermel , Ravikumar Ramachandran
IPC分类号： C23G1/10 , H01L21/02 , H01L21/28 , H01L21/3213 , C23G1/02 , H01L21/302 , H01L21/3205 , H01L21/461 , H01L21/4763
CPC分类号： H01L21/02071 , C23G1/106 , H01L21/28079 , H01L21/28088 , H01L21/32136
摘要： A process and composition for cleaning debris from a stack etch/ion implanted CMOS device which includes a tungsten gate conductor. The composition includes sulfuric acid and hydrogen peroxide in a volume ratio of at least about 6:1. In the process the composition contacts the CMOS device at atmospheric pressure and a temperature of between about 70° C. and about 90° C.
摘要翻译：用于从包括钨栅导体的叠层蚀刻/离子注入CMOS器件清洁碎屑的工艺和组合物。该组合物包括体积比为至少约6:1的硫酸和过氧化氢。在该过程中，组合物在大气压和约70℃至约90℃的温度下接触CMOS器件。

26. 发明申请

US20050017282A1 DRAM BURIED STRAP PROCESS WITH SILICON CARBIDE 审中-公开
标题翻译：具有碳化硅的DRAM烧结带工艺
公开(公告)号：US20050017282A1
公开(公告)日：2005-01-27
申请号：US10604488
申请日：2003-07-25
申请人： David Dobuzinsky , Jonathan Faltermeier , Philip Flaitz , Rajarao Jammy , Yuko Ninomiya , Ravikumar Ramachandran , Viraj Sardesai , Yun Wang
发明人： David Dobuzinsky , Jonathan Faltermeier , Philip Flaitz , Rajarao Jammy , Yuko Ninomiya , Ravikumar Ramachandran , Viraj Sardesai , Yun Wang
IPC分类号： H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10829 , H01L29/66181
摘要： In the process of forming a trench capacitor, the conductive strap connecting the center electrode of the capacitor with a circuit element in the substrate, such as the pass transistor of a DRAM cell, is separated from the crystalline substrate material by a barrier layer of silicon carbide formed during the process of etching the material within the trench, such as an oxide collar, using a reactive ion etch process with an etchant gas that contains carbon, such as C4F8.
摘要翻译：在形成沟槽电容器的过程中，将电容器的中心电极与衬底中的电路元件（例如DRAM单元的传输晶体管）连接的导电带通过硅的阻挡层与晶体衬底材料分离在蚀刻沟槽内的材料（例如氧化物环）的过程中形成的碳化物，其使用具有包含碳的蚀刻剂气体如C4F8的反应离子蚀刻工艺。

27. 发明申请

US20130256802A1 Replacement Gate With Reduced Gate Leakage Current 审中-公开
标题翻译：降低闸门泄漏电流的更换门
公开(公告)号：US20130256802A1
公开(公告)日：2013-10-03
申请号：US13430755
申请日：2012-03-27
申请人： Hemanth Jagannathan , Ramachandra Divakaruni , Unoh Kwon , Vijay Narayanan , Ravikumar Ramachandran
发明人： Hemanth Jagannathan , Ramachandra Divakaruni , Unoh Kwon , Vijay Narayanan , Ravikumar Ramachandran
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L21/28518 , H01L21/26506 , H01L21/28088 , H01L21/28176 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/105 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.
摘要翻译：提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。任选地，可以在通道中引入碳掺杂。

28. 发明授权

US08426300B2 Self-aligned contact for replacement gate devices 有权
公开(公告)号：US08426300B2
公开(公告)日：2013-04-23
申请号：US12958607
申请日：2010-12-02
申请人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
发明人： Ravikumar Ramachandran , Ying Li , Richard S. Wise
IPC分类号： H01L21/00
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7833 , H01L29/7843
摘要： A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure.

29. 发明申请

US20130015580A1 REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTURE 有权
标题翻译：替代金属门结构和制造方法
公开(公告)号：US20130015580A1
公开(公告)日：2013-01-17
申请号：US13180842
申请日：2011-07-12
申请人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
发明人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
摘要翻译：提供替代的金属栅极结构及其制造方法。所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。该方法还包括调整高k电介质材料的衬垫的高度。所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

30. 发明申请

US20120132998A1 Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current 失效
标题翻译：替代金属栅极结构提供工作功能和栅极泄漏电流的独立控制
公开(公告)号：US20120132998A1
公开(公告)日：2012-05-31
申请号：US12954946
申请日：2010-11-29
申请人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
发明人： Unoh Kwon , Ramachandra Divakaruni , Siddarth A. Krishnan , Ravikumar Ramachandran
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L27/092 , H01L21/28088 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L27/088 , H01L27/0922 , H01L29/49 , H01L29/513 , H01L29/66545 , H01L29/7833 , H01L29/7843
摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.
摘要翻译：可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

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