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21. 发明授权

US06282615B1 Multiprocessor system bus with a data-less castout mechanism 失效
标题翻译：具有无数据丢弃机制的多处理器系统总线
公开(公告)号：US06282615B1
公开(公告)日：2001-08-28
申请号：US09437044
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1202
CPC分类号： G06F12/0811 , G06F12/0804
摘要： A method and apparatus for casting out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. In response to a castout write request from a cache memory to a non-inclusive lower-level cache memory within a cache memory hierarchy, the data transfer is aborted if the lower-level cache memory already has a copy of the data of the castout write. The coherency state of the lower-level cache memory is then updated, if necessary.
摘要翻译：公开了一种用于在数据处理系统的高速缓存存储器层级内投出数据的方法和装置。数据处理系统具有多个处理单元，每个处理单元具有多级高速缓冲存储器层级。响应于从缓存存储器到高速缓存存储器层次结构内的非包容性低级高速缓冲存储器的丢弃写入请求，如果低级高速缓冲存储器已经具有写入数据的数据的副本，则中止数据传输。如果需要，则更新低级缓存的相关性状态。

22. 发明授权

US06408362B1 Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data 失效
标题翻译：数据处理系统，缓存和方法，以响应缓存数据的存储器副本的延迟来选择一个castout受害者
公开(公告)号：US06408362B1
公开(公告)日：2002-06-18
申请号：US09339402
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/127 , G06F12/0813 , G06F12/123
摘要： A data processing system includes a processing unit, a distributed memory including a local memory and a remote memory having differing access latencies, and a cache coupled to the processing unit and to the distributed memory. The cache includes a congruence class containing a plurality of cache lines and a plurality of latency indicators that each indicate an access latency to the distributed memory for a respective one of the cache lines. The cache further includes a cache controller that selects a cache line in the congruence class as a castout victim in response to the access latencies indicated by the plurality of latency indicators. In one preferred embodiment, the cache controller preferentially selects as castout victims cache lines having relatively short access latencies.
摘要翻译：数据处理系统包括处理单元，包括本地存储器的分布式存储器和具有不同访问延迟的远程存储器，以及耦合到处理单元和分布式存储器的高速缓存。高速缓存包括包含多个高速缓存行和多个等待时间指示符的一致等级，每个等待时间指示符指示针对相应一个高速缓存行的分布式存储器的访问等待时间。高速缓存还包括高速缓存控制器，其响应于由多个等待时间指示符指示的接入延迟，选择同余类中的高速缓存行作为转播牺牲者。在一个优选实施例中，高速缓存控制器优先选择具有相对短的访问延迟的丢弃受害缓存行。

23. 发明授权

US06345341B1 Method of cache management for dynamically disabling O state memory-consistent data 有权
标题翻译：用于动态禁用O状态内存一致性数据的缓存管理方法
公开(公告)号：US06345341B1
公开(公告)日：2002-02-05
申请号：US09339407
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system includes an interconnect, a plurality of processing units coupled to the interconnect, and at least one system memory and a plurality of caches coupled to the plurality of processing units. A cache suitable for use in such a data processing system includes data storage containing multiple granules of data and a number of state fields associated with the granules of data. Each state field has a plurality of possible states including an O state indicating that an associated granule is consistent with corresponding data in the memory and has unknown coherency with respect to peer caches in the data processing system. The cache updates the state field from the O state to another of the plurality of states in response to a snooped transaction on the interconnect.
摘要翻译：多处理器数据处理系统包括互连，耦合到互连的多个处理单元以及耦合到多个处理单元的至少一个系统存储器和多个高速缓存。适用于这种数据处理系统的高速缓存包括包含多个数据颗粒和与数据颗粒相关联的多个状态字段的数据存储。每个状态字段具有多个可能状态，包括指示相关联的粒子与存储器中的对应数据一致的O状态，并且与数据处理系统中的对等高速缓存具有未知的一致性。响应于互连上的窥探事务，高速缓存将状态字段从O状态更新为多状态中的另一状态。

24. 发明授权

US06298416B1 Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system 失效
标题翻译：用于在数据处理系统的分级高速缓存存储器架构内发送控制信号的方法和装置
公开(公告)号：US06298416B1
公开(公告)日：2001-10-02
申请号：US09437040
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
IPC分类号： G06F1208
CPC分类号： G06F12/0897
摘要： A method and apparatus for transmitting control signals within a hierarchial cache memory architecture of a data processing system is disclosed. The cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to an upper cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.
摘要翻译：公开了一种用于在数据处理系统的分级高速缓冲存储器架构内发送控制信号的方法和装置。高速缓存存储器层次结构包括多级缓存存储器，每个级别可以具有不同的大小和速度。响应于处理器对信息的请求，控制命令被发送到高速缓冲存储器层次结构。控制命令包括多个控制块。从高速缓存存储器层次结构的最低可能缓存级开始，确定高速缓存存储器层级的当前级别是否存在高速缓存命中。响应于在当前级别没有高速缓存命中的确定，在对应于当前级别的控制块从控制命令中移除之后，将缩写控制命令发送到高速缓存存储器层次结构的高级缓存级别。

25. 发明授权

US06553463B1 Method and system for high speed access to a banked cache memory 失效
标题翻译：用于高速访问存储缓存的方法和系统
公开(公告)号：US06553463B1
公开(公告)日：2003-04-22
申请号：US09436959
申请日：1999-11-09
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F12/0846 , G06F2212/6082
摘要： A method and system for high speed data access of a banked cache memory. In accordance with the method and system of the present invention, during a first cycle, in response to receipt of a request address at an access controller, the request address is speculatively transmitted to a banked cache memory, where the speculative transmission has at least one cycle of latency. Concurrently, the request address is snooped in a directory associated with the banked cache memory. Thereafter, during a second cycle the speculatively transmitted request address is distributed to each of multiple banks of memory within the banked cache memory. In addition, the banked cache memory is provided with a bank indication indicating which bank of memory among the multiple banks of memory contains the request address, in response to a bank hit from snooping the directory. Thereafter, data associated with the request address is output from the banked cache memory, in response to the bank indication, such that access time to a high latency remote banked cache memory is minimized.
摘要翻译：一种用于高速缓存存储器的高速数据访问的方法和系统。根据本发明的方法和系统，在第一周期期间，响应于在访问控制器处接收到请求地址，请求地址被推测地发送到存储的高速缓冲存储器，其中推测传输具有至少一个延迟周期。同时，请求地址被窥探在与存储的高速缓冲存储器相关联的目录中。此后，在第二周期期间，推测性发送的请求地址被分配到分组缓存存储器内的多个存储器组中的每一个。此外，为了响应于窥探目录的银行命中，所述存储体高速缓存存储器具有指示多个存储器组中的存储器组包含请求地址的存储体指示。此后，响应于存储体指示，从存储的高速缓冲存储器输出与请求地址相关联的数据，使得到高等待时间的远程分组高速缓冲存储器的访问时间被最小化。

26. 发明授权

US06425058B1 Cache management mechanism to enable information-type dependent cache policies 失效
标题翻译：缓存管理机制，使信息类型相关缓存策略
公开(公告)号：US06425058B1
公开(公告)日：2002-07-23
申请号：US09390186
申请日：1999-09-07
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr.
IPC分类号： G06F1206
CPC分类号： G06F12/121
摘要： A set associative cache includes a cache controller, a directory, and an array including at least one congruence class containing a plurality of sets. The plurality of sets are partitioned into multiple groups according to which of a plurality of information types each set can store. The sets are partitioned so that at least two of the groups include the same set and at least one of the sets can store fewer than all of the information types. The cache controller then implements different cache policies for at least two of the plurality of groups, thus permitting the operation of the cache to be individually optimized for different information types.
摘要翻译：集合关联高速缓存包括高速缓存控制器，目录和包括至少一个包含多个集合的同余类的数组。多个集合根据每个集合可以存储的多个信息类型中的哪一个被划分为多个组。这些集合被分区，使得至少两个组包括相同的集合，并且集合中的至少一个可以存储少于所有信息类型的集合。然后，高速缓存控制器为多个组中的至少两个实现不同的高速缓存策略，从而允许高速缓存的操作针对不同的信息类型单独优化。

27. 发明授权

US06434668B1 Method of cache management to store information in particular regions of the cache according to information-type 失效
标题翻译：缓存管理方法根据信息类型将信息存储在缓存的特定区域
公开(公告)号：US06434668B1
公开(公告)日：2002-08-13
申请号：US09390187
申请日：1999-09-07
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr.
IPC分类号： G06F1206
CPC分类号： G06F12/0864 , G06F12/0848 , G06F12/10 , G06F12/127
摘要： A set associative cache includes a number of congruence classes that each contain a plurality of sets, a directory, and a cache controller. The directory indicates, for each congruence class, which of a plurality of information types each of the plurality of sets can store. At least one set in at least one of the congruence classes is restricted to storing fewer than all of the information types and at least one set can store multiple information types. When the cache receives information to be stored of a particular information type, the cache controller stores the information into one of the plurality of sets indicated by the directory as capable of storing that particular information type. By managing the sets in which sets information is stored according to information type, an awareness of the characteristics of the various information types can easily be incorporated into the cache's allocation and victim selection policies.
摘要翻译：集合关联高速缓存包括多个等同类，每个等同类包含多个集合，目录和高速缓存控制器。目录指示对于每个同余类，多个集合中的每一个可以存储多个信息类型中的哪一个。至少一个等同类中的至少一个被限制为存储少于所有信息类型，并且至少一个集合可以存储多种信息类型。当高速缓存接收到要存储的特定信息类型的信息时，高速缓存控制器将信息存储为能够存储该特定信息类型的目录指示的多个集合中的一个集合。通过根据信息类型管理集信息的集合，可以容易地将各种信息类型的特征的意识并入到高速缓存的分配和受害者选择策略中。

28. 发明授权

US06405290B1 Multiprocessor system bus protocol for O state memory-consistent data 有权
标题翻译：多处理器系统总线协议，用于O状态内存一致的数据
公开(公告)号：US06405290B1
公开(公告)日：2002-06-11
申请号：US09339404
申请日：1999-06-24
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0862 , G06F2212/6028
摘要： A data processing system includes an interconnect, a system memory and a number of snoopers coupled to the interconnect, and response logic. In response to a requesting snooper issuing a data request on the interconnect specifying a memory address, the snoopers provide snoop responses. The response logic compiles the snoop responses to obtain a combined response including an indication of a demand-source snooper that will source requested data associated with the memory address to the requesting snooper and an indication of whether additional non-requested data will be supplied to the requesting snooper. This combined response is then transmitted to the snoopers on the interconnect to direct the provision of the requested data, and possibly unrequested prefetch data, to the requesting snooper.
摘要翻译：数据处理系统包括互连，系统存储器和耦合到互连的多个窥探器以及响应逻辑。响应于请求窥探者在互连上发布指定存储器地址的数据请求，窥探者提供窥探响应。响应逻辑编译窥探响应以获得组合响应，该组合响应包括要求源窥探者的指示，该请求源窥探者将向请求窥探者发送与存储器地址相关联的所请求数据，以及是否将附加的未请求数据提供给请求窥探者。然后将该组合的响应发送到互连上的窥探者，以将请求的数据的提供以及可能的未请求的预取数据引导到请求窥探者。

29. 发明授权

US06338116B1 Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system 失效
标题翻译：用于数据处理系统的高速缓存存储器层级内的无数据写入操作的方法和装置
公开(公告)号：US06338116B1
公开(公告)日：2002-01-08
申请号：US09437043
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0811
摘要： A method and apparatus for casing out data within a cache memory hierarchy for a data processing system is disclosed. The data processing system has multiple processing units, each of the processing units having a multi-level cache memory hierarchy. The cache memory hierarchy includes a first cache and a second cache at a same cache level. Furthermore, the first cache and the second cache share a lower-level cache. In response to a castout write request from the first cache to the lower-level cache, the second cache aborts the data transfer for the castout write request if the second cache already has a copy of data of the castout write request. The coherency state of both the first and second caches are then updated.
摘要翻译：公开了一种用于在数据处理系统的高速缓冲存储器层级内套出数据的方法和装置。数据处理系统具有多个处理单元，每个处理单元具有多级高速缓冲存储器层级。高速缓冲存储器层级包括在相同高速缓存级别的第一高速缓存和第二高速缓存。此外，第一缓存和第二高速缓存共享下级缓存。响应于从第一缓存到下级缓存的丢弃写入请求，如果第二高速缓冲存储器已经具有丢弃写入请求的数据的副本，则第二缓存器将中止写入请求的数据传输。然后更新第一和第二高速缓存的一致性状态。

30. 发明授权

US06467030B1 Method and apparatus for forwarding data in a hierarchial cache memory architecture 失效
标题翻译：用于在分层缓存存储器架构中转发数据的方法和装置
公开(公告)号：US06467030B1
公开(公告)日：2002-10-15
申请号：US09435962
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , James Stephen Fields, Jr. , Sanjeev Ghai , Praveen S. Reddy
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6022
摘要： A method and apparatus for forwarding data in a hierarchial cache memory architecture is disclosed. A cache memory hierarchy includes multiple levels of cache memories, each level having a different size and speed. A command is initially issued from a processor to the cache memory hierarchy. If the command is a Demand Load command, data corresponding to the Demand Load command is immediately forwarded from a cache having the data to the processor. Otherwise, if the command is a Prefetch Load command, data corresponding to the Prefetch Load command is held in a cache reload buffer within a cache memory preceding the processor.
摘要翻译：公开了一种用于在分级高速缓冲存储器架构中转发数据的方法和装置。高速缓冲存储器层级包括多级缓存存储器，每级具有不同的大小和速度。命令最初从处理器发出到高速缓存存储器层次结构。如果命令是Demand Load命令，则与Demand Load命令相对应的数据将立即从具有数据的缓存转发到处理器。否则，如果命令是预取加载命令，则与预取加载命令对应的数据保存在处理器之前的高速缓存中的缓存重新加载缓冲区中。

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