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21. 发明授权

US06496921B1 Layered speculative request unit with instruction optimized and storage hierarchy optimized partitions 失效
标题翻译：分层推测请求单元，具有指令优化和存储层次结构优化分区
公开(公告)号：US06496921B1
公开(公告)日：2002-12-17
申请号：US09345643
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F930
CPC分类号： G06F9/30047 , G06F9/3802 , G06F9/3885 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。

22. 发明授权

US06421762B1 Cache allocation policy based on speculative request history 有权
标题翻译：基于推测请求历史记录的缓存分配策略
公开(公告)号：US06421762B1
公开(公告)日：2002-07-16
申请号：US09345713
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/0897 , G06F12/126 , G06F2212/6024
摘要： A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value. The prefetch limit of cache usage may be established with a maximum number of sets in a congruence class usable by the requesting processing unit. A flag in a directory of the cache may be set to indicate that the prefetch value was retrieved as the result of a prefetch operation. In the implementation wherein the cache is a multi-level cache, a second flag in the cache directory may be set to indicate that the prefetch value has been sourced to an upstream cache. A cache line containing prefetch data can be automatically invalidated after a preset amount of time has passed since the prefetch value was requested.
摘要翻译：一种操作计算机系统的处理单元的方法，通过从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取值。高速缓存使用的预取限制可以由请求处理单元可用的同余类中的最大数量的集合来建立。高速缓存目录中的标志可以被设置为指示作为预取操作的结果检索预取值。在其中缓存是多级高速缓存的实现中，高速缓存目录中的第二标志可以被设置为指示预取值已经被提供给上游高速缓存。包含预取数据的缓存行可以在从请求预取值开始经过预设的时间后自动失效。

23. 发明授权

US06374333B1 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention 失效
标题翻译：缓存一致性协议，其中使用加载指令提示位来指示由干预提供的修改的高速缓存行的释放
公开(公告)号：US06374333B1
公开(公告)日：2002-04-16
申请号：US09437176
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

24. 发明授权

US06345343B1 Multiprocessor system bus protocol with command and snoop responses for modified-unsolicited cache state 有权
标题翻译：多处理器总线协议，包括读取请求，其具有在提供所请求的修改值时具有指定解除分配的襟翼
公开(公告)号：US06345343B1
公开(公告)日：2002-02-05
申请号：US09437178
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

25. 发明授权

US06662216B1 Fixed bus tags for SMP buses 失效
标题翻译：用于SMP总线的固定总线标签
公开(公告)号：US06662216B1
公开(公告)日：2003-12-09
申请号：US08839478
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

26. 发明授权

US06507880B1 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens 失效
标题翻译：总线协议，总线主机和总线监听器，用于执行使用多个令牌的全局操作
公开(公告)号：US06507880B1
公开(公告)日：2003-01-14
申请号：US09435927
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.
摘要翻译：响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

27. 发明授权

US06502171B1 Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data 失效
标题翻译：具有组合侦听响应的多处理器系统总线显式通知窥探者围绕数据
公开(公告)号：US06502171B1
公开(公告)日：2002-12-31
申请号：US09368231
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译：组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务或目标数据。具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

28. 发明授权

US06502168B1 Cache having virtual cache controller queues 失效
标题翻译：缓存具有虚拟缓存控制器队列
公开(公告)号：US06502168B1
公开(公告)日：2002-12-31
申请号：US09404028
申请日：1999-09-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

29. 发明授权

US06430683B1 Processor and method for just-in-time delivery of load data via time dependency field 失效
标题翻译：通过时间依赖性字段即时传送负载数据的处理器和方法
公开(公告)号：US06430683B1
公开(公告)日：2002-08-06
申请号：US09344023
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3838 , G06F12/0855 , G06F12/0859 , G06F13/4217
摘要： A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates an architected time dependency bit field of a load instruction to create a Distance of Dependency (DoD) bit field. The DoD bit field holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by the DoD bit field. In the preferred embodiment, an acknowledgement is sent to the processing unit when the time specified is available in the RTOQ.
摘要翻译：用于加载指令的时间执行的系统。更具体地，该系统实现了由加载指令请求的数据的及时传送。该系统由处理器，具有对应的L1高速缓存控制器的L1数据高速缓存器和指令处理器组成。指令处理器操纵负载指令的架构化时间依赖性位字段以创建依赖距离（DoD）位字段。 DoD位域保持相对依赖性值，该值用于对L1高速缓存控制器的相对时间排序队列（RTOQ）中的加载指令进行排序。加载指令在特定时间从RTOQ发送到L1数据高速缓存，以便在DoD位字段指定的时间从L1数据高速缓存中加载请求的数据。在优选实施例中，当指定的时间在RTOQ中可用时，确认被发送到处理单元。

30. 发明授权

US06425090B1 Method for just-in-time delivery of load data utilizing alternating time intervals 失效
标题翻译：使用交替时间间隔即时传送负载数据的方法
公开(公告)号：US06425090B1
公开(公告)日：2002-07-23
申请号：US09338946
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayanan Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F104
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3838 , G06F9/384
摘要： A method for converting a distance of dependency (DoD) value to a cycle of dependency (CoD) value is disclosed. The method comprises the steps of (i) simulating a dependency system timer (DST) on a data processing system, with the DST having a present time measured in cycles and a period, (ii) adding a DoD value of N bits to the present time to yield a resulting time of the least significant N bits of said adding step, and (iii) creating the CoD value by appending a carry over of the adding step to the resulting time, where when the carry over is not equal to zero, the carry over signals a user of the CoD value to wait until a next period before the CoD value should be applied. In one embodiment, the carry-over value is added to the value corresponding to a respective alternating period to yield an even/odd bit which determines the period.
摘要翻译：公开了将依赖距离（DoD）值转换为依赖循环（CoD）值的方法。该方法包括以下步骤：（i）在数据处理系统上模拟依赖系统定时器（DST），其中DST具有以周期和周期测量的当前时间，（ii）向目前添加N位的DoD值时间以产生所述相加步骤的最低有效N比特的结果时间，以及（iii）通过将加法步骤的进位附加到所得到的时间来创建CoD值，其中当进位不等于零时，进位信号指示CoD值的用户等待直到应用CoD值之前的下一个周期。在一个实施例中，结转值被加到对应于相应交替周期的值，以产生确定周期的偶数/奇数位。

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