专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06982043B1 Scatterometry with grating to observe resist removal rate during etch 有权
标题翻译：用光栅进行散射测量以观察蚀刻期间的抗蚀剂去除率
公开(公告)号：US06982043B1
公开(公告)日：2006-01-03
申请号：US10382181
申请日：2003-03-05
申请人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
发明人： Ramkumar Subramanian , Bharath Rangarajan , Catherine B. Labelle , Bhanwar Singh , Christopher F. Lyons
IPC分类号： B44C1/22
CPC分类号： H01L22/12 , H01L22/26
摘要： Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.
摘要翻译：公开了用于监测经历蚀刻工艺的图案化光致抗蚀剂包覆晶片结构的系统和方法。该系统包括半导体晶片结构，其包括衬底，覆盖衬底的一个或多个中间层和覆盖中间层的第一图案化光致抗蚀剂层，半导体晶片结构通过光致抗蚀剂层中的一个或多个开口进行蚀刻; 晶片蚀刻光刻胶监测系统被编程为随着蚀刻工艺的进行获得与光致抗蚀剂层有关的数据; 与晶片结构对准并与监视系统结合使用的图案特定光栅，光栅具有与第一图案化光致抗蚀剂层相同的间距和临界尺寸中的至少一个; 以及晶片处理控制器，可操作地连接到所述监控系统并且适于从所述监控系统接收数据，以便确定随后的晶片清洁过程的调整。

22. 发明授权

US06771356B1 Scatterometry of grating structures to monitor wafer stress 失效
标题翻译：光栅结构的散射法监测晶片应力
公开(公告)号：US06771356B1
公开(公告)日：2004-08-03
申请号：US10050626
申请日：2002-01-16
申请人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
发明人： Christopher F. Lyons , Bhanwar Singh , Steven C. Avanzino , Khoi A. Phan , Bharath Rangarajan , Ramkumar Subramanian , Cyrus E. Tabery
IPC分类号： G01B1116
CPC分类号： G01B11/165
摘要： A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.
摘要翻译：提供了一种用于监视制造工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个光栅。从光栅反射的光被处理收集的光的测量系统收集。所收集的光指示由于晶片的各个部分处的应力引起的变形。测量系统向处理器提供失真/应力相关数据，该处理器确定晶片各部分的失真的可接受性。收集的光可以通过散射测量系统进行分析，以产生与失真相关联的散射仪签名并产生可用于控制半导体制造过程的前馈控制信息。

23. 发明授权

US06589711B1 Dual inlaid process using a bilayer resist 有权
标题翻译：使用双层抗蚀剂的双镶嵌工艺
公开(公告)号：US06589711B1
公开(公告)日：2003-07-08
申请号：US09824696
申请日：2001-04-04
申请人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
发明人： Ramkumar Subramanian , Christopher F. Lyons , Marina V. Plat , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： There is provided a method of making a dual inlaid via in a first layer. The first layer may be a polymer intermetal dielectric, such as HSQ, of a semiconductor device. The method includes forming a first opening, such as a via, in the first layer and forming a bilayer resist in the first opening. The bilayer resist includes an imaging layer above a bottom antireflective coating (BARC). The imaging layer is selectively exposed to radiation such that no radiation reaches the lower section of the BARC in the first opening through the upper section of the BARC. The bilayer resist is pattered, and a second opening, such as a trench, is formed in communication with the first opening using the patterned bilayer resist as a mask.
摘要翻译：提供了在第一层中制作双重嵌入通孔的方法。第一层可以是半导体器件的聚合物金属间电介质，例如HSQ。该方法包括在第一层中形成诸如通孔的第一开口，并在第一开口中形成双层抗蚀剂。双层抗蚀剂包括底部抗反射涂层（BARC）上方的成像层。成像层选择性地暴露于辐射，使得在通过BARC的上部的第一开口中没有辐射到达BARC的下部。双层抗蚀剂被图案化，并且使用图案化双层抗蚀剂作为掩模，形成与第一开口连通的第二开口，例如沟槽。

24. 发明授权

US06187666B1 CVD plasma process to fill contact hole in damascene process 有权
标题翻译： CVD等离子体工艺在镶嵌工艺中填充接触孔
公开(公告)号：US06187666B1
公开(公告)日：2001-02-13
申请号：US09328148
申请日：1999-06-08
申请人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
发明人： Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan , Christopher F. Lyons , Sanjay K. Yedur , Ramkumar Subramanian
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/312 , H01L21/76831 , H01L2221/1063
摘要： The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
摘要翻译：本发明涉及在绝缘材料层中制造互连线和通孔的方法。在绝缘材料层中形成通孔。形成保护材料以至少与通孔的边缘和侧壁共形，所述保护材料有助于屏蔽通孔的至少边缘和侧壁至沟槽蚀刻步骤。执行沟槽蚀刻步骤以在绝缘材料中形成沟槽开口。通孔和沟槽填充有导电金属。

25. 发明授权

US08007631B2 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权
标题翻译：用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合
公开(公告)号：US08007631B2
公开(公告)日：2011-08-30
申请号：US11741991
申请日：2007-04-30
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23C10/00 , C29C59/02 , C03C17/22
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

26. 发明授权

US07384569B1 Imprint lithography mask trimming for imprint mask using etch 有权
标题翻译：使用蚀刻的压印掩模的压印光刻掩模修剪
公开(公告)号：US07384569B1
公开(公告)日：2008-06-10
申请号：US10909464
申请日：2004-08-02
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01L21/30 , H01L21/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.
摘要翻译：公开了光刻系统和方法，更具体地说，增强了印迹掩模特征分辨率的系统和方法。方面产生反馈信息，其通过采用散射测量系统来检测分辨率增强需求，以及通过修剪蚀刻程序减小压印掩模特征尺寸并增加印迹掩模的分辨率，从而有助于控制印迹掩模特征尺寸和分辨率。

27. 发明申请

US20070283883A1 SYSTEM AND METHOD FOR IMPRINT LITHOGRAPHY TO FACILITATE DUAL DAMASCENE INTEGRATION WITH TWO IMPRINT ACTS 有权
标题翻译：系统和方法，用于绘制两幅印刷动画的双重增强整合
公开(公告)号：US20070283883A1
公开(公告)日：2007-12-13
申请号：US11741991
申请日：2007-04-30
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23C10/00
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

28. 发明授权

US07295288B1 Systems and methods of imprint lithography with adjustable mask 有权
标题翻译：带可调面罩的压印光刻系统和方法
公开(公告)号：US07295288B1
公开(公告)日：2007-11-13
申请号：US11000869
申请日：2004-12-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
发明人： Ramkumar Subramanian , Bhanwar Singh , Khoi A. Phan
IPC分类号： G03B27/62 , G03B27/02 , G03B27/20
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.
摘要翻译：提供了通过调节压印光刻掩模的光栅特征来考虑晶片的表面变化的系统和方法。这种调节使用压电元件作为掩模的一部分，其可以在经受电压时改变尺寸（例如，高度变化）和/或移动。因此，通过调节施加到压电元件的电压量，可以获得这些元件的受控膨胀，以适应晶片表面的形貌变化。

29. 发明授权

US07235474B1 System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权
标题翻译：用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合
公开(公告)号：US07235474B1
公开(公告)日：2007-06-26
申请号：US10838612
申请日：2004-05-04
申请人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
发明人： Srikanteswara Dakshina-Murthy , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/44
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译：提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。

30. 发明授权

US07158896B1 Real time immersion medium control using scatterometry 失效
标题翻译：实时浸入介质控制采用散射法
公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译：公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。已知的光栅结构被构建在衬底上。实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式