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21. 发明授权

US08433706B2 Preference stack 有权
标题翻译：偏好堆栈
公开(公告)号：US08433706B2
公开(公告)日：2013-04-30
申请号：US13110764
申请日：2011-05-18
申请人： Geoffrey Wade , Mark Reyes , Henry Nguyen , Christopher Ploski
发明人： Geoffrey Wade , Mark Reyes , Henry Nguyen , Christopher Ploski
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06Q30/02 , G06F17/30554
摘要： Systems and methods for customizing the display of a set of data using a preference stack interface. The preference stack interface allows a user to interact with an ordered list of criterion objects. Each criterion object corresponds to an attribute of the data set to be presented to the user. In response to a change in the order of the criterion objects in the preference stack, a rendering of the dataset can be updated to differently and visually emphasize items according to which criterion objects each item meets.
摘要翻译：使用偏好堆栈接口自定义显示一组数据的系统和方法。偏好堆栈接口允许用户与标准对象的有序列表进行交互。每个标准对象对应于要呈现给用户的数据集的属性。响应于偏好堆叠中的标准对象的顺序的改变，可以不同地更新数据集的呈现，并且根据每个项目满足哪个标准对象在视觉上强调项目。

22. 发明申请

US20130000890A1 Multiple Sectioned Wire-Wrapped Screens 有权
标题翻译：多段包线屏
公开(公告)号：US20130000890A1
公开(公告)日：2013-01-03
申请号：US13170608
申请日：2011-06-28
申请人： Peter Olenick , Henry Nguyen , Robert Hodge , Ronnie Royer
发明人： Peter Olenick , Henry Nguyen , Robert Hodge , Ronnie Royer
IPC分类号： E03B3/18 , B21F33/00
CPC分类号： E21B43/084 , B01D29/111 , B01D29/48 , E21B43/086 , E21B43/088 , Y10T29/49604
摘要： Operators manufacture a wellscreen by forming a wire-wrapped screen on a base pipe. Rather than stopping and restarting winding, the desired length of screen is completed along the base pipe, and then the wire screen is segmented into a plurality of screen sections as required for the various zones and details of the implementation. Operators arrange the screen sections relative to one another on the base pipe, which can have different lengths with and without perforations. On the free ends of these separate screen sections, mating split ring components fit around the free ends and the base pipes. Male edges of one split ring component mate to complementary female edges of another to form the end ring around the screen section and base pipe, and longitudinal welds made in seams along the mating edges affix the split ring components together.
摘要翻译：操作员通过在基管上形成线缠绕的屏幕来制造井眼屏。不是停止并重新启动绕线，而是沿基管完成所需的屏幕长度，然后根据各个区域的要求将丝网分割成多个屏部分，并且实现细节。操作者在基管上相对于彼此布置屏幕部分，其可具有不同长度，具有和不具有穿孔。在这些分离的筛分部分的自由端上，配合的分隔环部件配合在自由端和基管周围。一个开口环部件的公边缘与另一个开口环部件的互补母边缘配合，以形成围绕筛分部分和底部管道的端环，并且沿着配合边缘沿接缝形成的纵向焊缝将裂口环部件固定在一起。

23. 发明申请

US20110289077A1 PREFERENCE STACK 有权
标题翻译：优先级堆栈
公开(公告)号：US20110289077A1
公开(公告)日：2011-11-24
申请号：US13110764
申请日：2011-05-18
申请人： Geoffrey Wade , Mark Reyes , Henry Nguyen , Christopher Ploski
发明人： Geoffrey Wade , Mark Reyes , Henry Nguyen , Christopher Ploski
IPC分类号： G06F17/30
CPC分类号： G06Q30/02 , G06F17/30554
摘要： Systems and methods for customizing the display of a set of data using a preference stack interface. The preference stack interface allows a user to interact with an ordered list of criterion objects. Each criterion object corresponds to an attribute of the data set to be presented to the user. In response to a change in the order of the criterion objects in the preference stack, a rendering of the dataset can be updated to differently and visually emphasize items according to which criterion objects each item meets.
摘要翻译：使用偏好堆栈接口自定义显示一组数据的系统和方法。偏好堆栈接口允许用户与标准对象的有序列表进行交互。每个标准对象对应于要呈现给用户的数据集的属性。响应于偏好堆叠中的标准对象的顺序的改变，可以不同地更新数据集的呈现，并且根据每个项目满足哪个标准对象在视觉上强调项目。

24. 发明授权

US07663939B2 Voltage stabilizer memory module 有权
标题翻译：稳压器内存模块
公开(公告)号：US07663939B2
公开(公告)日：2010-02-16
申请号：US11442818
申请日：2006-05-30
申请人： Henry Nguyen , Ngoc Le
发明人： Henry Nguyen , Ngoc Le
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C5/04 , G11C11/4074
摘要： A memory module is disclosed. The memory module comprises a voltage supply; a memory interface coupled to the voltage supply; a plurality of memory components; and a voltage stabilizer converter (VSC) coupled to the memory interface and to the plurality of memory components, the VSC for ensuring that the plurality of memory components operate at their optimum performance level. A voltage stabilizer memory module (VSMM) in accordance with the present invention includes a printed circuit board (PCB) that contains memory chips, discrete components, a voltage stabilizer converter, and other related components. The voltage stabilizer converter uses system voltage supply as its input and its output is the voltage supply for the DRAM components. Accordingly, the VSSM is more adaptable, more stable and has better performance than conventional memory modules.
摘要翻译：公开了一种存储器模块。存储器模块包括电压源; 耦合到电压源的存储器接口; 多个存储器组件; 以及耦合到存储器接口和多个存储器组件的稳压器转换器（VSC），VSC用于确保多个存储器组件以其最佳性能水平运行。根据本发明的稳压器存储器模块（VSMM）包括包含存储器芯片的印刷电路板（PCB），分立元件，稳压器转换器和其它相关元件。稳压器转换器采用系统电压作为输入，其输出为DRAM组件的电源。因此，VSSM比传统的内存模块更适应，更稳定，性能更好。

25. 发明申请

US20070024356A1 Methods and apparatus of managing a power amplifier 有权
标题翻译：管理功率放大器的方法和装置
公开(公告)号：US20070024356A1
公开(公告)日：2007-02-01
申请号：US11191571
申请日：2005-07-28
申请人： Leroy Plymale , Joseph Clark , Henry Nguyen , John Ruppel , Thomas Sears , Ronald Porco , Armando Jimenez
发明人： Leroy Plymale , Joseph Clark , Henry Nguyen , John Ruppel , Thomas Sears , Ronald Porco , Armando Jimenez
IPC分类号： H03F1/14
CPC分类号： H03F1/0277 , H03F1/0288
摘要： In the present technique for power management of a power amplifier, an amplifier bank from a plurality of amplifier banks in a power amplifier that has been switched off for a longest period of time is assessed (826) to provide a lowest amplifier bank. With this lowest amplifier bank, an up-threshold that is associated to the lowest amplifier bank is assessed (828), followed by another assessment (820) of a current power output of the power amplifier. It is next determined (830) whether the current power output corresponds at least in a predetermined way to the up-threshold, and if so, the lowest amplifier bank is accordingly switched on (832).
摘要翻译：在用于功率放大器的功率管理的现有技术中，评估了已经被关闭最长时间段的功率放大器中的多个放大器组的放大器组（826）以提供最低放大器组。利用这个最低的放大器组，评估与最低放大器组相关联的上限阈值（828），接着是功率放大器当前功率输出的另一个评估（820）。接下来确定（830）当前功率输出是否至少以预定方式对应于上限阈值，如果是，则最小放大器组相应地被接通（832）。

26. 发明申请

US20060267172A1 Memory-Module Board Layout for Use With Memory Chips of Different Data Widths 有权
标题翻译：内存模块板布局，用于不同数据宽度的内存芯片
公开(公告)号：US20060267172A1
公开(公告)日：2006-11-30
申请号：US10908718
申请日：2005-05-24
申请人： Henry Nguyen , Mark Burlington
发明人： Henry Nguyen , Mark Burlington
IPC分类号： H01L23/02
CPC分类号： G11C5/04 , G11C8/12 , G11C2029/1804 , H01L2924/0002 , H05K1/181 , H05K2201/09245 , H05K2201/09954 , H05K2201/10689 , H05K2203/1572 , Y02P70/611 , H01L2924/00
摘要： A memory module substrate printed-circuit board (PCB) has multi-type footprints and an edge connector for mating with a memory module socket on a motherboard. Two or more kinds of dynamic-random-access memory (DRAM) chips with different data I/O widths can be soldered to solder pads around the multi-type footprints. When ×4 DRAM chips with 4 data I/O pins are soldered over the multi-type footprints, the memory module has a rank-select signal that drives chip-select inputs to all DRAM chips. When ×8 DRAM chips with 8 data I/O pins are soldered over the multi-type footprints, the memory module has two rank-select signals. One rank-select drives chip-select inputs to front-side DRAM chips while the second rank-select drives chip-select inputs to back-side DRAM chips. Wiring traces on the PCB cross-over data nibbles between the solder pads and the connector to allow two ×4 chips to drive a byte driven by only one ×8 chip.
摘要翻译：存储器模块基板印刷电路板（PCB）具有多种类型的印迹和用于与主板上的存储器模块插座配合的边缘连接器。可以将具有不同数据I / O宽度的两种或更多种动态随机存取存储器（DRAM）芯片焊接到多类型脚印周围的焊盘。当具有4个数据I / O引脚的x4 DRAM芯片通过多种封装焊接时，存储器模块具有驱动芯片选择输入到所有DRAM芯片的等级选择信号。当具有8个数据I / O引脚的x8 DRAM芯片通过多种封装焊接时，存储器模块具有两个等级选择信号。一级选择驱动芯片选择输入到前端DRAM芯片，而第二级选择驱动芯片选择输入到后端DRAM芯片。 PCB交叉数据上的接线迹线在焊盘和连接器之间勉强化，以允许两个x4芯片驱动一个仅由一个x8芯片驱动的字节。

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