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21. 发明授权

US08334177B2 Methods for forming isolated fin structures on bulk semiconductor material 有权
标题翻译：在体半导体材料上形成隔离鳍结构的方法
公开(公告)号：US08334177B2
公开(公告)日：2012-12-18
申请号：US13278010
申请日：2011-10-20
申请人： Witold Maszara , Hemant Adhikari
发明人： Witold Maszara , Hemant Adhikari
IPC分类号： H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.
摘要翻译：提供了制造半导体器件的方法。一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

22. 发明授权

US06492209B1 Selectively thin silicon film for creating fully and partially depleted SOI on same wafer 失效
标题翻译：选择性薄的硅膜，用于在同一晶圆上产生完全和部分耗尽的SOI
公开(公告)号：US06492209B1
公开(公告)日：2002-12-10
申请号：US09607629
申请日：2000-06-30
申请人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
发明人： Srinath Krishnan , Matthew Buynoski , Witold Maszara
IPC分类号： H01L21302
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.
摘要翻译：一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。至少一个沟槽被蚀刻到体半导体晶片中。然后将晶片填充绝缘材料并抛光至半导体晶片的表面水平以形成大致平坦的表面。提供具有基底层和绝缘层的处理晶片。半导体晶片的平面被接合到处理晶片的绝缘层上。半导体晶片的沟槽填充区域形成第一厚度的区域，并且半导体晶片的其余区域形成第二厚度的区域。然后可以在第一厚度的区域中形成完全耗尽的晶体管器件，并且可以在第二厚度的区域中形成部分耗尽的晶体管器件。

23. 发明授权

US06284608B1 Method for making accumulation mode N-channel SOI 有权
标题翻译：用于制作累积模式N沟道SOI的方法
公开(公告)号：US06284608B1
公开(公告)日：2001-09-04
申请号：US09496245
申请日：2000-02-01
申请人： Zoran Krivakapic , Srinath Krishnan , Witold Maszara
发明人： Zoran Krivakapic , Srinath Krishnan , Witold Maszara
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/78696
摘要： A method of manufacturing an accumulation mode n-channel Silicon On Insulator (SOI) transistor includes forming an intrinsic silicon body region implanted with two deep Boron and one shallow Phosphorous implants; forming source/drain regions each implanted with Arsenic; and forming p-type regions adjacent each of the source and drain regions and disposed along the transistor channel. The SOI transistor has a higher transconductance than known SOI devices.
摘要翻译：一种制造堆积模式n沟道绝缘体（SOI）晶体管的方法包括：形成植入两个深硼和一个浅磷植入物的本征硅体区域; 形成每个植入砷的源/漏区; 以及在所述源极和漏极区域中的每一个附近形成并且沿着所述晶体管沟道布置的p型区域。 SOI晶体管具有比已知SOI器件更高的跨导。

24. 发明授权

US5965917A Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects 有权
标题翻译： SOI MOSFET中体接触形成的结构和方法，以浮现浮体效应
公开(公告)号：US5965917A
公开(公告)日：1999-10-12
申请号：US225248
申请日：1999-01-04
申请人： Witold Maszara , Srinath Krisnan
发明人： Witold Maszara , Srinath Krisnan
IPC分类号： H01L21/336 , H01L29/417 , H01L29/786 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66772 , H01L29/41733 , H01L29/78615
摘要： A silicon-on-insulator MOSFET includes a silicon layer and an insulator layer positioned over a silicon substrate. An isolation region defines a silicon region positioned over the insulator layer. The silicon region further includes a source region, a drain region, and a doped body region. The drain region and source region do not extend to the bottom of the silicon region. A first metal conductor is electrically coupled to the side and top of the source region and the side of the body region. The first metal conductor establishes a potential at the body region to control floating body effects. A second metal conductor is electrically coupled to the top of the drain region.
摘要翻译：绝缘体上硅MOSFET包括硅层和位于硅衬底上的绝缘体层。隔离区域限定位于绝缘体层上方的硅区域。硅区还包括源极区，漏极区和掺杂体区。漏极区域和源极区域不延伸到硅区域的底部。第一金属导体电耦合到源区域和身体区域的侧面的侧面和顶部。第一金属导体在身体区域建立一个潜力来控制浮体效应。第二金属导体电耦合到漏区的顶部。

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