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21. 发明授权

US07573078B2 Wide bandgap transistors with multiple field plates 有权
标题翻译：具有多个场板的宽带隙晶体管
公开(公告)号：US07573078B2
公开(公告)日：2009-08-11
申请号：US10976422
申请日：2004-10-29
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L29/778
CPC分类号： H01L29/404 , H01L29/2003 , H01L29/7787
摘要： A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.
摘要翻译：一种晶体管，包括在衬底上的多个有源半导体层，源极和漏极与半导体层接触。在源极和漏极之间以及多个半导体层上形成栅极。多个场板布置在半导体层之上，每个场板从栅极的边缘延伸到漏极，并且其中的每一个与所述半导体层和场板的其它层隔离。场板的最顶端电连接到源电极，而另外的场板电连接到栅极或源电极。

22. 发明申请

US20070205433A1 Insulating gate AlGaN/GaN HEMTs 审中-公开
标题翻译：绝缘栅AlGaN / GaN HEMT
公开(公告)号：US20070205433A1
公开(公告)日：2007-09-06
申请号：US11799786
申请日：2007-05-03
申请人： Primit Parikh , Umesh Mishra , Yifeng Wu
发明人： Primit Parikh , Umesh Mishra , Yifeng Wu
IPC分类号： H01L21/338 , H01L29/06
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/517 , H01L29/518 , H01L29/7783 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.
摘要翻译：公开了具有薄AlGaN层的AlGaN / GaN HEMT以减少陷阱并且还具有附加层以减少栅极泄漏并增加最大驱动电流。根据本发明的一个HEMT包括其上具有阻挡半导体层的高电阻率半导体层。阻挡层具有比高电阻率层更宽的带隙，并且层之间形成2DEG。源极和漏极触点接触阻挡层，阻挡层的一部分表面被触点覆盖。绝缘层包括在阻挡层的未覆盖表面上，并且绝缘层上包括栅极接触。绝缘层对栅极漏电流形成屏障，也有助于增加HEMT的最大电流驱动。本发明还包括用于制造根据本发明的HEMT的方法。在一种方法中，HEMT及其绝缘层使用金属有机化学气相沉积（MOCVD）制造。在另一种方法中，在溅射室中将绝缘层溅射到HEMT的顶表面上。

23. 发明申请

US20070059873A1 Fabrication of single or multiple gate field plates 有权
标题翻译：制造单栅极或多栅极场板
公开(公告)号：US20070059873A1
公开(公告)日：2007-03-15
申请号：US10570964
申请日：2004-09-09
申请人： Alessandro Chini , Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Alessandro Chini , Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L21/8238
CPC分类号： H01L29/404 , H01L27/0605 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/401 , H01L29/402 , H01L29/41766 , H01L29/42312 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/785
摘要： A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
摘要翻译：使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

24. 发明申请

US20050006669A1 Group III nitride based flip-chip integrated circuit and method for fabricating 有权
标题翻译： III族氮化物倒装芯片集成电路及其制造方法
公开(公告)号：US20050006669A1
公开(公告)日：2005-01-13
申请号：US10916819
申请日：2004-08-11
申请人： Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L21/8252 , H01L23/14 , H01L23/367 , H01L23/66 , H01L27/06 , H01L29/20 , H01L29/778 , H01L27/10
CPC分类号： H05K1/0206 , H01L21/8252 , H01L23/147 , H01L23/367 , H01L23/3677 , H01L23/66 , H01L27/0605 , H01L29/2003 , H01L29/7787 , H01L2224/16235 , H01L2224/16238 , H01L2224/1703 , H01L2224/73253 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/10329 , H01L2924/12032 , H01L2924/14 , H01L2924/1423 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19105 , H01L2924/30105 , H05K1/181 , H05K2201/066 , Y10T29/4913 , H01L2924/0002 , H01L2924/00
摘要： A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals. The present invention is particularly applicable to Group III nitride based active semiconductor devices grown on SiC substrates. The passive components and interconnects can then be formed on a lower cost, higher diameter wafer made of GaAs or Si. After separation, the Group III devices can be flip-chip mounted on the GaAs or Si substrate.
摘要翻译：公开了一种用于制造集成电路的倒装芯片集成电路和方法。根据本发明的方法包括在晶片上形成多个有源半导体器件并分离有源半导体器件。无源元件和互连形成在电路基板的表面上，并且通过电路基板形成至少一个导电通孔。至少一个有源半导体器件被倒装芯片安装在电路基板上，其中至少一个接合焊盘与导电通孔之一电接触。根据本发明的倒装芯片集成电路包括在一个表面上具有无源部件和互连的电路基板，并且可以具有通过其的导电通孔。有源半导体器件被倒装安装在电路基板上，所述至少一个通孔中的一个与该器件的至少一个端子中的一个接触。本发明特别适用于在SiC衬底上生长的III族氮化物基有源半导体器件。然后可以在GaAs或Si制成的较低成本，更高直径的晶圆上形成无源部件和互连。分离后，III组器件可以倒装安装在GaAs或Si衬底上。

25. 发明授权

US09419124B2 Insulating gate AlGaN/GaN HEMT 有权
公开(公告)号：US09419124B2
公开(公告)日：2016-08-16
申请号：US11356791
申请日：2006-02-17
申请人： Primit Parikh , Umesh Mishra , Yifeng Wu
发明人： Primit Parikh , Umesh Mishra , Yifeng Wu
IPC分类号： H01L31/0328 , H01L31/0336 , H01L29/778 , H01L29/51 , H01L23/29 , H01L23/31 , H01L29/20 , H01L29/43
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.

26. 发明授权

US08575651B2 Devices having thick semi-insulating epitaxial gallium nitride layer 有权
标题翻译：具有厚半绝缘外延氮化镓层的器件
公开(公告)号：US08575651B2
公开(公告)日：2013-11-05
申请号：US11103117
申请日：2005-04-11
申请人： Adam William Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Peter Smith , Scott T. Sheppard
发明人： Adam William Saxler , Yifeng Wu , Primit Parikh , Umesh Mishra , Richard Peter Smith , Scott T. Sheppard
IPC分类号： H01L31/072
CPC分类号： H01L21/0254 , H01L21/0237 , H01L21/02425 , H01L21/02439 , H01L21/02491 , H01L21/02581 , H01L21/0262 , H01L29/1608 , H01L29/2003 , H01L29/4175 , H01L29/41766 , H01L29/66462 , H01L29/7787
摘要： Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.
摘要翻译：提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。半绝缘或绝缘GaN外延层具有至少约4μm的厚度。还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

27. 发明授权

US08274159B2 Group III nitride based flip-chip integrated circuit and method for fabricating 有权
标题翻译： III族氮化物倒装芯片集成电路及其制造方法
公开(公告)号：US08274159B2
公开(公告)日：2012-09-25
申请号：US12951372
申请日：2010-11-22
申请人： Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H01L23/48 , H01L23/34
CPC分类号： H05K1/0206 , H01L21/8252 , H01L23/147 , H01L23/367 , H01L23/3677 , H01L23/66 , H01L27/0605 , H01L29/2003 , H01L29/7787 , H01L2224/16235 , H01L2224/16238 , H01L2224/1703 , H01L2224/73253 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01042 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/10329 , H01L2924/12032 , H01L2924/14 , H01L2924/1423 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19105 , H01L2924/30105 , H05K1/181 , H05K2201/066 , Y10T29/4913 , H01L2924/0002 , H01L2924/00
摘要： A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device.
摘要翻译：电路基板在第一表面上具有一个或多个有源部件和多个无源电路元件。有源半导体器件具有材料层和多个端子的衬底。有源半导体器件被倒装芯片安装在电路基板上，并且器件的至少一个端子与电路基板上的有源元件电连接。基板上的有源元件和安装有倒装芯片的有源半导体器件与无源电路元件组合形成前置放大器和输出放大器。在电源开关配置中，电路基板在第一表面上具有逻辑控制电路。安装在电路基板上的半导体晶体管倒装芯片电连接到第一表面上的控制电路，从而控制倒装芯片安装器件的接通和断开。

28. 发明授权

US08169005B2 High voltage GaN transistors 有权
标题翻译：高压GaN晶体管
公开(公告)号：US08169005B2
公开(公告)日：2012-05-01
申请号：US13014619
申请日：2011-01-26
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/94
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

29. 发明授权

US07692263B2 High voltage GaN transistors 有权
标题翻译：高压GaN晶体管
公开(公告)号：US07692263B2
公开(公告)日：2010-04-06
申请号：US11603427
申请日：2006-11-21
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/93
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

30. 发明申请

US20090315078A1 INSULATING GATE AlGaN/GaN HEMT 审中-公开
标题翻译：绝缘栅AlGaN / GaN HEMT
公开(公告)号：US20090315078A1
公开(公告)日：2009-12-24
申请号：US12554803
申请日：2009-09-04
申请人： Primit Parikh , Umesh Mishra , Yifeng Wu
发明人： Primit Parikh , Umesh Mishra , Yifeng Wu
IPC分类号： H01L29/778 , H01L29/06 , H01L29/772 , H01L29/12
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/2003 , H01L29/432 , H01L29/517 , H01L29/518 , H01L29/7783 , H01L29/7786 , H01L2924/0002 , H01L2924/00
摘要： AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a 2DEG forms between the layers. Source and drain contacts contact the barrier layer, with part of the surface of the barrier layer uncovered by the contacts. An insulating layer is included on the uncovered surface of the barrier layer and a gate contact is included on the insulating layer. The insulating layer forms a barrier to gate leakage current and also helps to increase the HEMT's maximum current drive. The invention also includes methods for fabricating HEMTs according to the present invention. In one method, the HEMT and its insulating layer are fabricated using metal-organic chemical vapor deposition (MOCVD). In another method the insulating layer is sputtered onto the top surface of the HEMT in a sputtering chamber.
摘要翻译：公开了具有薄AlGaN层的AlGaN / GaN HEMT以减少陷阱并且还具有附加层以减少栅极泄漏并增加最大驱动电流。根据本发明的一个HEMT包括其上具有阻挡半导体层的高电阻率半导体层。阻挡层具有比高电阻率层更宽的带隙，并且层之间形成2DEG。源极和漏极触点接触阻挡层，阻挡层的一部分表面被触点覆盖。绝缘层包括在阻挡层的未覆盖表面上，并且绝缘层上包括栅极接触。绝缘层对栅极漏电流形成屏障，也有助于增加HEMT的最大电流驱动。本发明还包括用于制造根据本发明的HEMT的方法。在一种方法中，HEMT及其绝缘层使用金属有机化学气相沉积（MOCVD）制造。在另一种方法中，在溅射室中将绝缘层溅射到HEMT的顶表面上。

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