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    • 21. 发明授权
    • Method for designing an integrated circuit defect monitor
    • 设计集成电路缺陷监视器的方法
    • US07093213B2
    • 2006-08-15
    • US10710940
    • 2004-08-13
    • John M. CohnLeah M. P. Pastel
    • John M. CohnLeah M. P. Pastel
    • G06F17/50G01R31/28
    • G06F17/505
    • A method and system for designing a test structure. The method including: defining and placing test circuit pins in an integrated circuit design; routing one or more fat wires, each fat wire routed between a set of the test circuit pins; processing each fat wire into a continuous wire and one or more corresponding wire segments adjacent to the continuous wire, the continuous wire separated from the one or more corresponding wire segments by a space; and connecting the continuous wire and the one or more wire segments to circuit elements of a defect monitor scan chain, the circuit elements previously inserted into the integrated circuit design.
    • 一种用于设计测试结构的方法和系统。 该方法包括:将集成电路设计中的测试电路引脚定义和放置; 布置一条或多条脂肪线,每条脂肪线在一组测试电路引脚之间布线; 将每个脂肪丝处理成连续的线和与所述连续线相邻的一个或多个对应的线段,所述连续线从所述一个或多个对应的线段与空间分离; 以及将连续线和一个或多个线段连接到缺陷监视器扫描链的电路元件,电路元件先前插入到集成电路设计中。