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21. 发明授权

US06804165B2 Latency time switch for an S-DRAM 失效
标题翻译： S-DRAM的延迟时间切换
公开(公告)号：US06804165B2
公开(公告)日：2004-10-12
申请号：US10374657
申请日：2003-02-26
申请人： Peter Schrögmeier , Stefan Dietrich , Sabine Kieser , Pramod Acharya
发明人： Peter Schrögmeier , Stefan Dietrich , Sabine Kieser , Pramod Acharya
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)
摘要翻译：用于产生用于通过S-DRAM的数据路径（38）进行同步数据传输的延迟数据使能信号的用于由高频时钟信号（CLK）计时的S-DRAM（1）的延迟时间电路具有可控等待时间发生器（57），用于以可调延迟时间延迟解码的外部数据使能信号（PAR），比较电路（60）比较高频时钟的周期时间（tcycle）信号（CLK），具有所述数据路径（38）的预定信号延迟时间，并且如果所述数据路径（38）的信号延迟时间大于所述延迟时间，则将所述等待时间发生器（57）的等待时间缩短循环时间时钟信号（CLK）的周期时间（tcycle）

22. 发明授权

US06388944B2 Memory component with short access time 有权
标题翻译：具有访问时间短的内存组件
公开(公告)号：US06388944B2
公开(公告)日：2002-05-14
申请号：US09773221
申请日：2001-01-31
申请人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
发明人： Peter Schrögmeier , Stefan Dietrich , Torsten Partsch , Thomas Hein , Patrick Heyne , Thilo Marx
IPC分类号： G11C800
CPC分类号： G11C7/1069
摘要： A memory chip with a short data access time limits the propagation time of a bit on local data line strips which are far away from output amplifiers by centering switches with respect to a center of the cell array strips, wherein the switches are junction points between local data lines and main data lines.
摘要翻译：具有短数据访问时间的存储器芯片通过相对于单元阵列条的中心对中开关来限制远离输出放大器的本地数据线条上的位的传播时间，其中开关是本地数据线和主数据线。

23. 发明授权

US06717886B2 Control circuit for an S-DRAM 有权
标题翻译：用于S-DRAM的控制电路
公开(公告)号：US06717886B2
公开(公告)日：2004-04-06
申请号：US10248874
申请日：2003-02-26
申请人： Acharya Pramod , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier , Christian Weis
发明人： Acharya Pramod , Stefan Dietrich , Sabine Kieser , Peter Schroegmeier , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C7/22 , G11C7/1072 , G11C8/18 , G11C11/4076
摘要： Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.
摘要翻译：用于由具有用于存储等待时间值的可编程模式寄存器的由高频时钟信号计时的S-DRAM的数据路径的控制电路; 延迟发生器，用于以可切换的等待时间延迟由内部序列控制器产生的数据路径控制信号; 延迟解码器，其以取决于存储在模式寄存器中的等待时间值的方式切换等待时间发生器，由至少一个信号延迟元件提供，其可由等待时间解码器切换并用于信号延迟具有特定延迟时间的数据路径控制信号，如果存储的等待时间值高，延迟解码器切换相关联的信号延迟元件。

24. 发明授权

US07224625B2 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US07224625B2
公开(公告)日：2007-05-29
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

25. 发明申请

US20050254307A1 Method and circuit arrangement for controlling write access to a semiconductor memory 有权
标题翻译：用于控制对半导体存储器的写访问的方法和电路装置
公开(公告)号：US20050254307A1
公开(公告)日：2005-11-17
申请号：US11117698
申请日：2005-04-29
申请人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Peter Schroegmeier , Christian Weis
IPC分类号： G11C7/00 , G11C7/10 , G11C7/22 , G11C11/34 , G11C11/407 , G11C11/4076 , G11C11/4096
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C11/4076 , G11C11/4096 , G11C2207/229
摘要： The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.
摘要翻译：本发明涉及一种用于控制对半导体存储器，特别是DDR图形存储器的写入访问的方法，其中多个数据分组被写入每个数据脉冲串的半导体存储器，其中写访问由写命令启动，要写入存储器的数据分组在数据选通写时钟控制信号的周期的控制下锁存，其中数据分组被交替地使用数据选通写时钟控制信号的相应下降沿和上升沿锁存，并且数据选通写时钟控制信号在写操作开始时具有定义的状态。本发明还涉及一种用于执行该方法的电路装置。

26. 发明授权

US06670802B2 Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits 有权
公开(公告)号：US06670802B2
公开(公告)日：2003-12-30
申请号：US10033131
申请日：2001-10-22
申请人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
发明人： Stefan Dietrich , Patrick Heyne , Thilo Marx , Sabine Kieser , Michael Sommer , Thomas Hein , Michael Markert , Torsten Partsch , Peter Schroegmeier , Christian Weis
IPC分类号： G01R3102
CPC分类号： G11C29/003
摘要： Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

27. 发明授权

US06532188B2 Integrated memory having a row access controller for activating and deactivating row lines 有权
公开(公告)号：US06532188B2
公开(公告)日：2003-03-11
申请号：US10012161
申请日：2001-10-29
申请人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
发明人： Stefan Dietrich , Thomas Hein , Patrick Heyne , Thilo Marx , Torsten Partsch , Sabine Kieser , Peter Schroegmeier , Michael Sommer , Christian Weis
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18
摘要： An integrated memory is described which has a memory cell array with column lines and row lines. A row access controller serves for activating one of the row lines and for controlling a deactivation operation. An input of a control unit is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data output is synchronized with a clock signal. In this case, the signal is adjustable depending on an operating frequency of the memory. An output signal of the control unit serves for triggering the deactivation operation of one of the row lines after a write access. Therefore, in the event of a write access, a comparatively high data throughput is possible even at different operating frequencies of the integrated memory.

28. 发明授权

US07848134B2 FB DRAM memory with state memory 有权
标题翻译： FB DRAM内存带状态存储器
公开(公告)号：US07848134B2
公开(公告)日：2010-12-07
申请号：US12178407
申请日：2008-07-23
申请人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
发明人： Milena Ivanov , Heinz Hoenigschmid , Stefan Dietrich , Michael Markert
IPC分类号： G11C11/24
CPC分类号： G11C11/4091 , G11C11/404 , G11C2211/4016
摘要： A memory chip with a plurality of FB DRAM cells, having a word line coupled to a first FB DRAM cell and a second FB DRAM cell is disclosed. The memory chip further has a first bit line coupled to the first FB DRAM cell, and a first state memory circuit coupled to the first bit line. The memory chip further includes a second bit line coupled to the second FB DRAM cell, and a second state memory circuit coupled to the second bit line. The memory chip further includes a sense amplifier, which can be coupled to the first FB DRAM cell, the second FB DRAM cell, the first state memory circuit or the second state memory circuit.
摘要翻译：公开了具有耦合到第一FB DRAM单元和第二FB DRAM单元的字线的具有多个FB DRAM单元的存储器芯片。存储器芯片还具有耦合到第一FB DRAM单元的第一位线和耦合到第一位线的第一状态存储器电路。存储器芯片还包括耦合到第二FB DRAM单元的第二位线和耦合到第二位线的第二状态存储器电路。存储器芯片还包括读出放大器，其可耦合到第一FB DRAM单元，第二FB DRAM单元，第一状态存储器电路或第二状态存储器电路。

29. 发明授权

US07797042B2 Device for applying a transcutaneous stimulus or for transcutaneous measuring of a parameter 有权
标题翻译：用于施用经皮刺激或经皮测量参数的装置
公开(公告)号：US07797042B2
公开(公告)日：2010-09-14
申请号：US11750495
申请日：2007-05-18
申请人： Stefan Dietrich , Timo Freitag
发明人： Stefan Dietrich , Timo Freitag
IPC分类号： A61N1/18
CPC分类号： A61H39/002 , A61H21/00 , A61H2201/1645 , A61H2205/027 , A61N1/0456 , A61N1/0541 , A61N1/32 , A61N1/36014 , A61N1/36036
摘要： The apparatus for transcutaneous stimulation or transcutaneous measurement of a parameter is a device which fits wholly within the pinna (external ear) of the vertebrate. In order to fit completely within the pinna, the housing is C-shaped and from each end of the housing is a curved section which has a spring action that holds the apparatus inside the ear. This apparatus has a compact design which allows for nerve stimulation in a particularly efficient, ergonomically favorable and easy manipulation for the patient.
摘要翻译：用于经皮刺激或经皮测量参数的装置是完全适合脊椎动物的针刺（外耳）的装置。为了完全配合在针刺内，壳体是C形的，并且从壳体的每个端部是弯曲部分，其具有将装置保持在耳朵内部的弹簧作用。该装置具有紧凑的设计，其能够以对患者特别有效的，符合人体工程学的有利且容易的操作来进行神经刺激。

30. 发明授权

US07633814B2 Memory device and method of operating such 失效
标题翻译：内存设备及操作方法
公开(公告)号：US07633814B2
公开(公告)日：2009-12-15
申请号：US11735928
申请日：2007-04-16
申请人： Paul Wallner , Stefan Dietrich , Peter Gregorius
发明人： Paul Wallner , Stefan Dietrich , Peter Gregorius
IPC分类号： G11C16/04
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1057 , G11C7/106 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A memory device comprising a memory cell array; an input circuit for receiving command data and providing drive signals to the memory cell array; an output buffer for buffering data read out from the memory cell array; and a timer for driving the output buffer such that the buffered data are provided at an output after a predetermined time interval has elapsed, the predetermined time interval beginning with the provision of the drive signals.
摘要翻译：一种存储器件，包括存储单元阵列; 用于接收命令数据并向存储单元阵列提供驱动信号的输入电路; 用于缓冲从存储单元阵列读出的数据的输出缓冲器; 以及用于驱动输出缓冲器的定时器，使得在经过预定时间间隔之后的输出处提供缓冲数据，从提供驱动信号开始的预定时间间隔。

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