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21. 发明授权

US08377792B2 Method of forming high capacitance semiconductor capacitors with a single lithography step 有权
标题翻译：用单光刻步骤形成高电容半导体电容器的方法
公开(公告)号：US08377792B2
公开(公告)日：2013-02-19
申请号：US12756097
申请日：2010-04-07
申请人： Peter J. Hopper , William French , Peter Smeys , Peter Johnson
发明人： Peter J. Hopper , William French , Peter Smeys , Peter Johnson
IPC分类号： H01L21/027 , H01L21/266
CPC分类号： H01L28/60 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： An interdigitated semiconductor capacitor with a large number of plates and a capacitance in the micro-farad range is formed on a wafer with only a single lithography step by depositing each odd layer of metal through a first shadow mask that lies spaced apart from the wafer, and each even layer of metal through a second shadow mask that lies spaced apart from the wafer.
摘要翻译：具有大量板和微法拉范围内的电容的交叉指向的半导体电容器仅在单个光刻步骤上形成在晶片上，通过沉积与晶片间隔开的第一荫罩，每个奇数层的金属，以及通过与晶片间隔开的第二荫罩的每个偶数金属层。

22. 发明授权

US08042260B2 Methods of forming inductors on integrated circuits 有权
标题翻译：在集成电路上形成电感器的方法
公开(公告)号：US08042260B2
公开(公告)日：2011-10-25
申请号：US12250385
申请日：2008-10-13
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , Andrei Papou
IPC分类号： H01F7/06
CPC分类号： H01L23/5227 , H01F17/0006 , H01F41/046 , H01L2924/0002 , Y10T29/4902 , Y10T29/49071 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913 , H01L2924/00
摘要： The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements.
摘要翻译：所要求保护的发明涉及在半导体衬底上形成一个或多个电感器的方法。在一个实施例中，公开了一种在包括集成电路的半导体衬底上形成电感器芯元件阵列的方法。第一组间隔开的金属芯元件形成在衬底上。然后在芯元件的侧表面上形成隔离侧壁。之后，在衬底上形成第二组金属芯元件。第一和第二组芯元件基本上是共面的和交错的，使得只有隔离侧壁分隔相邻的芯元件。具体实施例涉及其他处理操作，例如不同类型的金属的选择性电镀以形成核心元件和/或沉积和蚀刻离开隔离层以在核心元件上形成隔离侧壁。

23. 发明授权

US08004061B1 Conductive trace with reduced RF impedance resulting from the skin effect 失效
标题翻译：导电痕迹，由皮肤效应引起的RF阻抗降低
公开(公告)号：US08004061B1
公开(公告)日：2011-08-23
申请号：US10897901
申请日：2004-07-23
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L29/00
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).
摘要翻译：以千兆赫兹频率的金属迹线的射频（RF）阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个鳍片。当以具有多个环的螺旋构造形成时，金属迹线形成具有增加的品质因数（Q）的电感器。

24. 发明授权

US07531824B1 High value inductor with conductor surrounded by high permeability polymer formed on a semiconductor substrate 有权
标题翻译：具有由半导体衬底上形成的高磁导率聚合物包围的导体的高值电感器
公开(公告)号：US07531824B1
公开(公告)日：2009-05-12
申请号：US11274932
申请日：2005-11-14
申请人： Peter Johnson , Peter J. Hopper , Kyuwoon Hwang , William French
发明人： Peter Johnson , Peter J. Hopper , Kyuwoon Hwang , William French
IPC分类号： H01L29/02
CPC分类号： H01L23/5227 , H01L23/645 , H01L2924/0002 , H01L2924/12044 , H01L2924/19015 , H01L2924/00
摘要： An apparatus and method for fabricating high value inductors embedded on semiconductor integrated circuit. The apparatus and method involve forming a conductor on the semiconductor substrate. Once the conductor is formed, a polymer material is provided on the substrate surrounding the conductor. The polymer material contains a ferromagnetic material so that the permeability of the polymer is greater than one. In various embodiments, the ferromagnetic material may be any one of a number of different high permeable materials such as iron oxide, zinc, manganese, zirconium, samarium (SA), neodymium (NA), cobalt, nickel or a combination thereof.
摘要翻译：一种用于制造嵌入在半导体集成电路上的高值电感器的装置和方法。该装置和方法包括在半导体衬底上形成导体。一旦形成导体，在围绕导体的基底上提供聚合物材料。聚合物材料含有铁磁材料，使得聚合物的渗透性大于1。在各种实施方案中，铁磁材料可以是多种不同的高渗透性材料中的任何一种，例如氧化铁，锌，锰，锆，钐（SA），钕（NA），钴，镍或它们的组合。

25. 发明授权

US07463131B1 Patterned magnetic layer on-chip inductor 有权
标题翻译：图案磁性层片上电感
公开(公告)号：US07463131B1
公开(公告)日：2008-12-09
申请号：US11111660
申请日：2005-04-21
申请人： Kyuwoon Hwang , Peter J. Hopper , Robert Drury , Peter Johnson
发明人： Kyuwoon Hwang , Peter J. Hopper , Robert Drury , Peter Johnson
IPC分类号： H01F5/00
CPC分类号： H02M7/003 , H01F1/14708 , H01F17/0006 , H01F17/04 , H01F2017/0066 , H01F2017/008 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.
摘要翻译：片上电感器结构包括顶部和底部金属板，其形成为围绕形成在顶板和底板之间的导体线圈，但是通过介入材料与其分离。顶板和底板优选地由铁磁合金形成，例如，坡莫合金，并且被细分为多个间隔开的段，从而减少涡流。基于用于制造结构的工艺技术来优化段的数量。优选地，在顶板和底板之间形成有限的间隙，选择间隙的高度来调节结构的总电感。

26. 发明授权

US07301436B1 Apparatus and method for precision trimming of integrated circuits using anti-fuse bond pads 有权
标题翻译：使用反熔丝接合焊盘精密修整集成电路的装置和方法
公开(公告)号：US07301436B1
公开(公告)日：2007-11-27
申请号：US11274491
申请日：2005-11-14
申请人： Peter J. Hopper , Peter Johnson , Philipp Lindorfer
发明人： Peter J. Hopper , Peter Johnson , Philipp Lindorfer
IPC分类号： H01C13/00
CPC分类号： H01L23/5228 , H01L24/02 , H01L27/0802 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/05042 , H01L2924/14 , H01L2924/19043
摘要： An apparatus and method for using anti-fuse bond pads used to provide trimmed resistor values to the input terminals of circuits on an integrated circuit die. The apparatus and method comprises fabricating on a semiconductor integrated circuit a resistive network. The resistive network includes a first terminal, a second terminal and a resistor coupled between the two terminals. An anti-fuse bond pad and a trimming resistor are coupled between the first terminal and the second terminal. The trimming resistor is configured to be electrically coupled between the first terminal and the second terminal when a ball bond is formed on the anti-fuse bond pad. In various embodiments, a plurality of the anti-fuse bond pads and trimming resistors may be coupled between the two terminals. By selectively forming ball bonds on the plurality of anti-fuse bond pads, the resistance of the network can be selectively trimmed as needed.
摘要翻译：一种用于使用反熔丝接合焊盘的装置和方法，用于向集成电路管芯上的电路的输入端提供修整的电阻值。该装置和方法包括在半导体集成电路上制造电阻网络。电阻网络包括耦合在两个端子之间的第一端子，第二端子和电阻器。反熔丝接合焊盘和微调电阻耦合在第一端子和第二端子之间。当在反熔丝接合焊盘上形成球焊时，微调电阻被配置为电耦合在第一端子和第二端子之间。在各种实施例中，多个反熔丝接合焊盘和微调电阻器可以耦合在两个端子之间。通过在多个反熔丝接合焊盘上选择性地形成球键，可以根据需要选择性地修整网络的电阻。

27. 发明授权

US07250841B1 Saucer-shaped half-loop MEMS inductor with very low resistance 有权
标题翻译：碟形半环形MEMS电感器具有非常低的电阻
公开(公告)号：US07250841B1
公开(公告)日：2007-07-31
申请号：US11213155
申请日：2005-08-25
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
IPC分类号： H01F27/02
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49069 , Y10T29/49165 , H01L2924/00
摘要： A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
摘要翻译：微机电系统（MEMS）电感器形成为完全围绕由铁磁材料形成的磁芯结构的碟形形状。此外，可以通过将碟形MEMS电感器分成多个电隔离的MEMS电感器楔形物来形成MEMS电感器阵列。

28. 发明授权

US07223680B1 Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect 失效
标题翻译：形成双镶嵌金属痕迹的方法，由皮肤效应引起的RF阻抗降低
公开(公告)号：US07223680B1
公开(公告)日：2007-05-29
申请号：US10727451
申请日：2003-12-03
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L21/44
CPC分类号： H01L23/5227 , H01L21/76802 , H01L21/76838 , H01L23/5283 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
摘要翻译：以千兆赫兹频率的金属迹线的RF阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个指状物。当形成为具有多个环时，金属迹线形成具有增加的Q的电感器。

29. 发明授权

US07098044B1 Method of forming an etched metal trace with reduced RF impedance resulting from the skin effect 有权
标题翻译：形成由皮肤效应引起的具有降低的RF阻抗的蚀刻金属迹线的方法
公开(公告)号：US07098044B1
公开(公告)日：2006-08-29
申请号：US10759621
申请日：2004-01-16
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Michael Mian , Robert Drury
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L23/5227 , H01L23/5283 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
摘要翻译：以千兆赫兹频率的金属迹线的RF阻抗通过形成金属迹线而减小，以具有从基极区域延伸的基极区域和多个指状物。当形成为具有多个环时，金属迹线形成具有增加的Q的电感器。

30. 发明授权

US06586302B1 Method of using trenching techniques to make a transistor with a floating gate 有权
标题翻译：使用沟槽技术制造具有浮动栅极的晶体管的方法
公开(公告)号：US06586302B1
公开(公告)日：2003-07-01
申请号：US09931477
申请日：2001-08-16
申请人： Peter J. Hopper , Yuri Mirgorodski , Chin Miin Shyu , David Tsuei , Peter Johnson , Alexander H. Owens
发明人： Peter J. Hopper , Yuri Mirgorodski , Chin Miin Shyu , David Tsuei , Peter Johnson , Alexander H. Owens
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method for making an electrically programmable and erasable memory cell is disclosed. Specifically, a method for creating a floating gate using shallow trench isolation-type techniques is utilized to provide a floating gate having sharply defined tip characteristics. A first insulating layer is formed over a substrate. A conductive material is formed over the first insulating layer. A trench is defined in the conductive layer. This trench is filled with an oxide which is used as a mask to define tips of the floating gate during an etching process which defines the edges of the floating gate. After the floating gate has been etched, a tunneling oxide deposited over the floating gate. A conductive material is then formed over the tunneling oxide.
摘要翻译：公开了一种制造电可编程和可擦除存储单元的方法。具体地说，利用浅沟槽隔离型技术产生浮置栅极的方法用于提供具有尖锐定义的尖端特性的浮动栅极。第一绝缘层形成在衬底上。在第一绝缘层上形成导电材料。在导电层中限定沟槽。该沟槽填充有氧化物，其用作掩模以在限定浮动栅极的边缘的蚀刻工艺期间限定浮置栅极的尖端。在浮栅被蚀刻之后，沉积在浮栅上的隧道氧化物。然后在隧道氧化物上形成导电材料。

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