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21. 发明申请

US20080215821A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IN COHERENCY STATE 有权
标题翻译：数据处理系统和方法，用于高效率通信
公开(公告)号：US20080215821A1
公开(公告)日：2008-09-04
申请号：US12103564
申请日：2008-04-15
申请人： Jason F. Cantin , James S. Fields , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields , Steven R. Kunkel , William J. Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

22. 发明申请

US20080215819A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR A CACHE COHERENCY PROTOCOL STATE THAT PREDICTS LOCATIONS OF SHARED MEMORY BLOCKS 有权
标题翻译：用于预测共享存储块位置的高速缓存协议状态的方法，设备和计算机程序产品
公开(公告)号：US20080215819A1
公开(公告)日：2008-09-04
申请号：US12107350
申请日：2008-04-22
申请人： Jason Frederick Cantin , Steven R. Kunkel
发明人： Jason Frederick Cantin , Steven R. Kunkel
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is defined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory read requests to read data in a cache line that is not currently in the shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.
摘要翻译：公开了用于减少不必要地广播的本地请求的数量以减少从SMP计算机系统中的远程节点访问数据的等待时间的方法，装置和计算机程序产品。定义共享的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在共享高速缓存行中读取数据的存储器读取请求。当高速缓存行处于共享无效状态时，预测数据的有效副本位于本地节点中。当高速缓存行处于无效状态而不处于共享无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于共享无效状态的缓存行中读取数据的内存读取请求首先被广播到远程节点。在当前处于共享无效状态的高速缓存行中读取数据的存储器读取请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器读取请求，存储器读取请求被广播到远程节点。

23. 发明授权

US06839816B2 Shared cache line update mechanism 失效
标题翻译：共享缓存行更新机制
公开(公告)号：US06839816B2
公开(公告)日：2005-01-04
申请号：US10082868
申请日：2002-02-26
申请人： John Michael Borkenhagen , Steven R. Kunkel
发明人： John Michael Borkenhagen , Steven R. Kunkel
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0837 , G06F12/0831
摘要： Embodiments are provided in which cache updating is described for a computer system having at least a first processor and a second processor having a first cache and a second cache, respectively. When the second processor obtains from the first processor a lock to a shared memory region, the first cache pushes to the second cache cache lines for the addresses in the shared memory region accessed by the first processor while the first processor had the lock.

24. 发明授权

US06728842B2 Cache updating in multiprocessor systems 失效
标题翻译：多处理器系统中的缓存更新
公开(公告)号：US06728842B2
公开(公告)日：2004-04-27
申请号：US10061859
申请日：2002-02-01
申请人： Jeffrey D. Brown , Steven R. Kunkel , David A. Luick
发明人： Jeffrey D. Brown , Steven R. Kunkel , David A. Luick
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： Embodiments are provided in which cache update is implemented by using a counter table having a plurality of entries to keep track of different modified cache lines of a cache of a processor. If a cache line of the cache is modified by the processor and the original content of the cache line came from a cache of another processor, a counter in the counter table restarts and reaches a predetermined value (e.g., overflows) triggering the broadcast of the modified cache line so that the cache of the other processor can snarf a copy of the modified cache line. As a result, when the other processor reads from a memory address matching that of the cache line, the cache of the other processor already has the most current copy for the matching memory address to feed the processor. Therefore, a cache read miss is avoided and system performance is improved.
摘要翻译：提供了实施例，其中通过使用具有多个条目的计数器表来实现高速缓存更新，以跟踪处理器的高速缓存的不同修改的高速缓存行。如果高速缓存的高速缓存行被处理器修改，并且高速缓存行的原始内容来自另一个处理器的高速缓存，则计数器表中的计数器重新启动并达到触发广播的预定值（例如，溢出）修改的高速缓存行，使得其他处理器的缓存可以绕过修改的高速缓存行的副本。结果，当另一个处理器从与高速缓存行的存储器地址匹配的存储器地址读取时，另一个处理器的高速缓存器已经具有用于匹配存储器地址的最新的副本来馈送处理器。因此，避免了缓存读取缺失，提高了系统性能。

25. 发明授权

US6105051A Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor 失效
标题翻译：确保在多线程处理器中执行线程的进展的装置和方法
公开(公告)号：US6105051A
公开(公告)日：2000-08-15
申请号：US956875
申请日：1997-10-23
申请人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Steven R. Kunkel , Sheldon Bernard Levenstein , Andrew Henry Wottreng
发明人： John Michael Borkenhagen , Richard James Eickemeyer , William Thomas Flynn , Steven R. Kunkel , Sheldon Bernard Levenstein , Andrew Henry Wottreng
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/00
CPC分类号： G06F9/4843 , G06F9/3009 , G06F9/3851
摘要： A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.
摘要翻译：用于在数据处理系统中执行计算机处理操作的系统和方法包括多线程处理器和线程切换逻辑。多线程处理器能够在可独立执行的两条或更多条指令线之间进行切换。每个线程根据执行状态在线程状态寄存器中具有相应的状态。线程开关逻辑包含一个线程开关控制寄存器，用于存储发生线程的条件。线程开关逻辑具有超时寄存器，当多线程处理器中的活动线程的执行超过可编程时间段时，强制执行线程切换。线程开关逻辑还具有前进进程计数寄存器，以防止多线程处理器中的线程之间的重复线程切换。线程切换逻辑还响应于能够改变不同线程的优先级并从而取代线程切换事件的软件管理器。

26. 发明授权

US08874853B2 Local and global memory request predictor 有权
标题翻译：本地和全局内存请求预测器
公开(公告)号：US08874853B2
公开(公告)日：2014-10-28
申请号：US12793795
申请日：2010-06-04
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0813
摘要： A method, circuit arrangement, and design structure utilize broadcast prediction data to determine whether to globally broadcast a memory request in a computing system of the type that includes a plurality of nodes, each node including a plurality of processing units. The method includes updating broadcast prediction data for a cache line associated with a first memory request within a hardware-based broadcast prediction data structure in turn associated with a first processing unit in response to the first memory request, the broadcast prediction data for the cache line including data associated with a history of ownership of the cache line. The method further comprises accessing the broadcast prediction data structure and determining whether to perform an early broadcast of a second memory request to a second node based on broadcast prediction data within the broadcast prediction data structure in response to that second memory request associated with the cache line.
摘要翻译：一种方法，电路装置和设计结构利用广播预测数据来确定是否在包括多个节点的类型的计算系统中全局广播存储器请求，每个节点包括多个处理单元。所述方法包括响应于第一存储器请求，在基于硬件的广播预测数据结构中更新与第一存储器请求相关联的高速缓存行的广播预测数据，该第一存储器请求与第一处理单元相对应，用于高速缓存行的广播预测数据包括与高速缓存行的所有权历史相关联的数据。该方法还包括响应于与高速缓存行相关联的第二存储器请求，基于广播预测数据结构内的广播预测数据，来访问广播预测数据结构并确定是否对第二节点执行第二存储器请求的早期广播。

27. 发明授权

US08244988B2 Predictive ownership control of shared memory computing system data 有权
标题翻译：共享内存计算系统数据的预测所有权控制
公开(公告)号：US08244988B2
公开(公告)日：2012-08-14
申请号：US12432835
申请日：2009-04-30
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/528 , G06F12/0842 , G06F12/126 , G06F2212/1016
摘要： A method, circuit arrangement, and design structure utilize a lock prediction data structure to control ownership of a cache line in a shared memory computing system. In a first node among the plurality of nodes, lock prediction data in a hardware-based lock prediction data structure for a cache line associated with a first memory request is updated in response to that first memory request, wherein at least a portion of the lock prediction data is predictive of whether the cache line is associated with a release operation. The lock prediction data is then accessed in response to a second memory request associated with the cache line and issued by a second node and a determination is made as to whether to transfer ownership of the cache line from the first node to the second node based at least in part on the accessed lock prediction data.
摘要翻译：方法，电路布置和设计结构利用锁预测数据结构来控制共享存储器计算系统中的高速缓存行的所有权。在所述多个节点中的第一节点中，响应于所述第一存储器请求来更新与用于与第一存储器请求相关联的高速缓存行的基于硬件的锁预测数据结构中的预测数据锁定，其中所述锁的至少一部分预测数据预测高速缓存行是否与释放操作相关联。然后，锁定预测数据被响应于与高速缓存线相关联并由第二节点发出的第二存储器请求而被访问，并且基于在第二节点处是否将高速缓存行的所有权从第一节点转移到第二节点进行确定至少部分地基于所访问的锁定预测数据。

28. 发明授权

US08112587B2 Shared data prefetching with memory region cache line monitoring 有权
标题翻译：共享数据预取与内存区域缓存行监视
公开(公告)号：US08112587B2
公开(公告)日：2012-02-07
申请号：US12432823
申请日：2009-04-30
申请人： Jason F. Cantin , Steven R. Kunkel
发明人： Jason F. Cantin , Steven R. Kunkel
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F12/0813 , G06F12/0815 , G06F2212/6022
摘要： A method, circuit arrangement, and design structure for prefetching data for responding to a memory request, in a shared memory computing system of the type that includes a plurality of nodes, is provided. Prefetching data comprises, receiving, in response to a first memory request by a first node, presence data for a memory region associated with the first memory request from a second node that sources data requested by the first memory request, and selectively prefetching at least one cache line from the memory region based on the received presence data. Responding to a memory request comprises tracking presence data associated with memory regions associated with cached cache lines in the first node, and, in response to a memory request by a second node, forwarding the tracked presence data for a memory region associated with the memory request to the second node.
摘要翻译：提供了在包括多个节点的类型的共享存储器计算系统中的用于预取数据以响应存储器请求的方法，电路布置和设计结构。预取数据包括：响应于第一节点的第一存储器请求，接收来自第二节点的与第一存储器请求相关联的存储器区域的存在数据，该第二节点发送由第一存储器请求请求的数据，并且选择性地预取至少一个基于接收的存在数据从存储器区域的高速缓存行。响应于存储器请求包括跟踪与第一节点中与高速缓存行相关联的存储器区域的存在数据，并且响应于第二节点的存储器请求，转发与存储器请求相关联的存储器区域的跟踪存在数据到第二个节点。

29. 发明授权

US07747826B2 Data processing system and method for efficient communication utilizing an in coherency state 有权
标题翻译：用于在一致性状态下有效通信的数据处理系统和方法
公开(公告)号：US07747826B2
公开(公告)日：2010-06-29
申请号：US12103564
申请日：2008-04-15
申请人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
发明人： Jason F. Cantin , James S. Fields, Jr. , Steven R. Kunkel , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory, and the second coherency domain includes a coherent second cache memory. The first cache memory within the first coherency domain of the data processing system holds a memory block in a storage location associated with an address tag and a coherency state field. The coherency state field is set to a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is likely cached only within the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。第一相关域包括第一高速缓冲存储器，并且第二相干域包括相干第二高速缓冲存储器。数据处理系统的第一相干域内的第一高速缓冲存储器在与地址标签和一致性状态字段相关联的存储位置中保存存储器块。相关性状态字段被设置为指示地址标签有效的状态，存储位置不包含有效数据，并且该存储器块可能仅在第一相干域内被缓存。

30. 发明申请

US20080147987A1 METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR A CACHE COHERENCY PROTOCOL STATE THAT PREDICTS LOCATIONS OF MODIFIED MEMORY BLOCKS 有权
标题翻译：用于预测改进的存储块位置的高速缓存协议状态的方法，设备和计算机程序产品
公开(公告)号：US20080147987A1
公开(公告)日：2008-06-19
申请号：US11954742
申请日：2007-12-12
申请人： JASON FREDERICK CANTIN , Steven R. Kunkel
发明人： JASON FREDERICK CANTIN , Steven R. Kunkel
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813 , G06F2212/507
摘要： A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to reduce global traffic in an SMP computer system. A modified invalid cache coherency protocol state is defined that predicts whether a memory access request to read or write data in a cache line can be satisfied within a local node. When a cache line is in the modified invalid state, the only valid copies of the data are predicted to be located in the local node. When a cache line is in the invalid state and not in the modified invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory access requests to read exclusive or write data in a cache line that is not currently in the modified invalid state are broadcast first to all nodes. Memory access requests to read exclusive or write data in a cache line that is currently in the modified invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory access requests within the local node, the memory access requests are broadcast to the remote nodes.
摘要翻译：公开了一种方法，装置和计算机程序产品，用于减少不必要地广播的远程请求的数量，以减少从本地节点访问数据的等待时间并减少SMP计算机系统中的全局流量。定义了修改的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在高速缓存行中读取或写入数据的存储器访问请求。当缓存行处于修改的无效状态时，数据的唯一有效副本被预测位于本地节点中。当高速缓存行处于无效状态而不处于修改的无效状态时，预测数据的有效副本位于远程节点之一中。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到所有节点。在当前处于修改的无效状态的高速缓存行中读取独占或写入数据的存储器访问请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器访问请求，存储器访问请求广播到远程节点。

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