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21. 发明授权

US06602754B1 Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer 有权
标题翻译：氮注入到氮化物间隔物中以减少间隔物上的硅化镍形成
公开(公告)号：US06602754B1
公开(公告)日：2003-08-05
申请号：US10059039
申请日：2002-01-30
申请人： George J. Kluth , Minh Van Ngo , Paul R. Besser
发明人： George J. Kluth , Minh Van Ngo , Paul R. Besser
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/265
摘要： Bridging between silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by implanting the exposed surfaces of the silicon nitride sidewall spacers with nitrogen to create a surface region having an increased nitrogen concentration. Embodiments include implanting the silicon nitride sidewall spacers with nitrogen such that the nitrogen concentration of the exposed surface is increased by about 5% to about 15%, thereby substantially preventing the formation of metal silicide on the sidewall spacers.
摘要翻译：通过用氮气注入氮化硅侧壁间隔物的暴露表面以产生具有增加的氮浓度的表面区域来防止在栅电极上的硅化物层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。实施例包括用氮气注入氮化硅侧壁间隔物，使得暴露表面的氮浓度增加约5％至约15％，从而基本上防止在侧壁间隔物上形成金属硅化物。

22. 发明授权

US06528362B1 Metal gate with CVD amorphous silicon layer for CMOS devices and method of making with a replacement gate process 有权
标题翻译：具有用于CMOS器件的CVD非晶硅层的金属栅极和用替代栅极工艺制造的方法
公开(公告)号：US06528362B1
公开(公告)日：2003-03-04
申请号：US09691181
申请日：2000-10-19
申请人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
发明人： Paul R. Besser , Qi Xiang , Matthew S. Buynoski
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28061 , H01L29/4925 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a chemical vapor deposited layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the CVD amorphous silicon layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the CVD amorphous silicon layer.
摘要翻译：半导体结构及其制造方法在硅衬底上提供金属栅极。该栅极包括在该基板上的高介电常数和在该高k栅极电介质上的非晶硅化学气相沉积层。然后在CVD非晶硅层上形成金属。由于CVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同。

23. 发明授权

US06518154B1 Method of forming semiconductor devices with differently composed metal-based gate electrodes 有权
标题翻译：用不同组合的金属基栅极形成半导体器件的方法
公开(公告)号：US06518154B1
公开(公告)日：2003-02-11
申请号：US09813310
申请日：2001-03-21
申请人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
发明人： Matthew S. Buynoski , Qi Xiang , Paul R. Besser
IPC分类号： H01L213205
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： MOS transistors and CMOS devices comprising a plurality of transistors including metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal on a thin gate insulator layer extending over first and second active device (e.g., a MOS transistor) precursor regions of a semiconductor substrate; selectively forming at least one masking layer segment on the first blanket layer overlying selective ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or semi-metal, or silicon, over the thus-formed structure; effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying the other ones of the transistor precursor regions; exposing and selectively removing the masking layer segment; and simultaneously patterning the alloyed and unalloyed/unsilicided portions of the first blanket layer to form metal-based gate electrodes of different composition. The invention also includes MOS and CMOS devices comprising differently composed metal-based gate electrodes.
摘要翻译：包括多个晶体管的MOS晶体管和CMOS器件包括不同组成的金属基栅极，其方法包括：在第一和第二有源器件上延伸的薄栅极绝缘层上沉积第一金属的第一覆盖层（例如，，MOS晶体管）前驱体区域; 选择性地形成覆盖所述MOS晶体管前体区域中的选择性掩模层的所述第一覆盖层上的至少一个掩模层段; 在如此形成的结构上沉积第二金属或半金属或硅的第二覆盖层; 在覆盖晶体管前体区域中的另一层的第一和第二覆盖层的接触部分之间发生合金化或硅化反应; 曝光和选择性地去除掩模层段; 并且同时对第一覆盖层的合金化和非合金化/未硅化部分进行构图，以形成不同组成的金属基栅电极。本发明还包括包含不同组合的金属基栅极的MOS和CMOS器件。

24. 发明授权

US06514858B1 Test structure for providing depth of polish feedback 失效
标题翻译：提供抛光反馈深度的测试结构
公开(公告)号：US06514858B1
公开(公告)日：2003-02-04
申请号：US09829202
申请日：2001-04-09
申请人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
发明人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
IPC分类号： H01L214763
CPC分类号： H01L22/34 , B24B37/042 , B24B49/00 , H01L21/31053 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.
摘要翻译：提供了一种用于控制半导体器件的抛光工艺的测试结构。测试结构由结构层，第一处理层和互连构成。第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

25. 发明授权

US06444513B1 Metal gate stack with etch stop layer having implanted metal species 有权
标题翻译：具有蚀刻停止层的具有植入金属物质的金属栅极叠层
公开(公告)号：US06444513B1
公开(公告)日：2002-09-03
申请号：US09810348
申请日：2001-03-19
申请人： Paul R. Besser , Srikanteswara Dakshina-Murthy
发明人： Paul R. Besser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L218238
CPC分类号： H01L29/4966 , H01L21/28088 , Y10S438/947 , Y10S438/949
摘要： A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.
摘要翻译：金属栅结构及其形成方法将金属杂质引入例如由TiN制成的第一金属层中。这些杂质产生更大的蚀刻选择性的表面区域，其防止了在形成金属栅极结构期间在覆盖钨栅的蚀刻过程中TiN的过蚀刻。防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。提供铝或钽作为金属杂质提供了足够的蚀刻停止能力，并且不会不希望地影响TiN的功函数。

26. 发明授权

US06432805B1 Co-deposition of nitrogen and metal for metal silicide formation 有权
标题翻译：用于金属硅化物形成的氮和金属的共沉积
公开(公告)号：US06432805B1
公开(公告)日：2002-08-13
申请号：US09783620
申请日：2001-02-15
申请人： Eric N. Paton , Minh Van Ngo , Paul R. Besser
发明人： Eric N. Paton , Minh Van Ngo , Paul R. Besser
IPC分类号： H01L213205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e.g., Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.
摘要翻译：通过在氮气存在下首先沉积难熔金属（例如Ni）以形成金属氮化物层，以防止沉积的金属与氮化硅侧壁间隔物中的游离Si的反应，从而避免了氮化硅侧壁间隔物的剥离处理桥接在栅电极上的金属硅化物层和半导体器件的源极/漏极区域上的金属硅化物层之间。

27. 发明授权

US06368950B1 Silicide gate transistors 有权
标题翻译：硅化物栅极晶体管
公开(公告)号：US06368950B1
公开(公告)日：2002-04-09
申请号：US09734186
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28097
摘要： A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.
摘要翻译：实现自对准金属硅化物栅极的方法是通过将非晶硅限制在覆盖沟道的凹槽中并退火以使非晶硅与其上覆金属相互作用以形成自对准金属硅化物栅极来实现的。在沉积硅之前，在凹陷的底部和侧壁上形成由氧氮化物或氮化物/氧化物堆叠形成的栅极电介质层。除了凹部中硅的部分之外，除去硅。通过操纵金属和自对准金属硅化物栅之间的蚀刻选择性来去除金属的剩余部分。

28. 发明授权

US06342414B1 Damascene NiSi metal gate high-k transistor 有权
标题翻译：大马士革NiSi金属栅极高k晶体管
公开(公告)号：US06342414B1
公开(公告)日：2002-01-29
申请号：US09734189
申请日：2000-12-12
申请人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
发明人： Qi Xiang , Paul R. Besser , Matthew S. Buynoski , John C. Foster , Paul L. King , Eric N. Paton
IPC分类号： H01L218238
CPC分类号： H01L21/28194 , H01L21/28097 , H01L21/28114 , H01L29/495 , H01L29/4975 , H01L29/51 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.
摘要翻译：实现自对准低温金属硅化物栅极的方法是通过将低温硅化金属限制在覆盖沟道的凹槽内并进行退火以使低温硅化金属及其上覆的硅相互作用以形成自对准低温度金属硅化物门。进行平面化步骤以通过化学机械抛光除去剩余的未反应的硅，直到没有检测到硅。

29. 发明授权

US06329277B1 Method of forming cobalt silicide 有权
标题翻译：形成硅化钴的方法
公开(公告)号：US06329277B1
公开(公告)日：2001-12-11
申请号：US09417839
申请日：1999-10-14
申请人： Bill Yowjuang Liu , Paul R. Besser
发明人： Bill Yowjuang Liu , Paul R. Besser
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.
摘要翻译：形成硅化物区域的半导体布置和方法包括在硅衬底上共形沉积还原材料层。然后将难熔金属层共形沉积在还原材料层上。然后进行退火以在硅衬底上形成难熔金属硅化物层。金属硅化物层是硅化钴，还原材料层包括钽，镁，铝或钙中的至少一种。还原材料减少硅衬底上的自然氧化物以形成硅化钴。

30. 发明授权

US06297107B1 High dielectric constant materials as gate dielectrics 有权
标题翻译：高介电常数材料作为栅极电介质
公开(公告)号：US06297107B1
公开(公告)日：2001-10-02
申请号：US09691228
申请日：2000-10-19
申请人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
发明人： Eric Paton , Matthew S. Byunoski , Paul R. Besser , Paul L. King , Qi Xiang
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/31691 , H01L29/517 , H01L29/66545
摘要： A semiconductor structure having a gate dielectric between a gate electrode and a semiconductor substrate is formed with a high dielectric metal oxide layer by replacing a sacrificial gate oxide. Embodiments include forming the metal oxide layer by applying a chemical solution deposition of a metalorganic on to an exposed surface of the substrate followed by pyrolizing the metalorganic residue to a metal oxide.
摘要翻译：通过替代牺牲栅极氧化物，在栅电极和半导体衬底之间具有栅极电介质的半导体结构形成有高介电金属氧化物层。实施例包括通过将金属有机物的化学溶液沉积施加到基板的暴露表面上，然后将金属有机残渣热解成金属氧化物来形成金属氧化物层。

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