专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20120059576A1 METHOD, SYSTEM, APPARATUS AND COMPUTER-READABLE MEDIUM FOR BROWSING SPOT INFORMATION 有权
标题翻译：方法，系统，设备和计算机可读介质，用于浏览SPOT信息
公开(公告)号：US20120059576A1
公开(公告)日：2012-03-08
申请号：US13039314
申请日：2011-03-03
申请人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
发明人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
IPC分类号： G06F3/048 , G01C21/00
CPC分类号： G06F3/04842 , G01C21/00 , G01C21/3682 , G09B29/007
摘要： A method, a system, an apparatus, and a computer-readable medium for browsing spot information, adapted to an electronic device, are provided. In the present method, a plurality of spot information are retrieved, in which each of the spot information at least comprises a picture and a location of a spot. Next, an electronic map is displayed and a spot marker is marked at the spot location of each spot information on the electronic map. Meanwhile, a spot browsing bar is displayed on a side of the electronic map and the spot pictures of the spot information are sequentially displayed in the spot browsing bar. When a select operation of a certain spot marker on the electronic map is received, the spot browsing bar is scrolled to show the spot picture corresponding to the selected spot marker.
摘要翻译：提供了适用于电子设备的用于浏览点信息的方法，系统，装置和计算机可读介质。在本方法中，检索多个点信息，其中每个点信息至少包括图片和点的位置。接下来，显示电子地图，并且在电子地图上的每个点信息的点位置处标记点标记。同时，在电子地图的一侧显示现场浏览栏，并且在点浏览栏中顺序地显示点信息的照片。当接收到电子地图上的特定点标记的选择操作时，滚动显示浏览栏以显示与所选择的点标记对应的点图。

22. 发明申请

US20110293870A1 COMPOSITE COVER SHEET AND COVER SHEET ASSEMBLY 审中-公开
标题翻译：复合盖板和盖板组件
公开(公告)号：US20110293870A1
公开(公告)日：2011-12-01
申请号：US13113557
申请日：2011-05-23
申请人： Ming-Chuan LIN , Ping-Wen Huang , Shih-Cheng Wang , Chin-Liang Chen , Hsien-Ming Wu , Chen-Anne Chuang , Chien-Wen Chen , Hui-Chin Chen , Han-Chung Chen
发明人： Ming-Chuan LIN , Ping-Wen Huang , Shih-Cheng Wang , Chin-Liang Chen , Hsien-Ming Wu , Chen-Anne Chuang , Chien-Wen Chen , Hui-Chin Chen , Han-Chung Chen
IPC分类号： B32B33/00
CPC分类号： B32B7/06 , B29C63/0056 , B32B3/085 , B32B7/12 , B32B25/20 , B32B27/308 , B32B27/32 , B32B27/36 , B32B2250/03 , B32B2457/20 , B32B2457/208 , C09J7/20 , C09J2203/318 , C09J2433/00 , C09J2483/00 , Y10T428/1476 , Y10T428/1486 , Y10T428/149
摘要： A composite cover sheet includes a first protective film, a first adhesive layer, a second protective film and a second adhesive layer. The first protective film has a first sticking part and a first movable part. The first protective film is attached to a base sheet through the first adhesive layer, and the first protective film is removed from the base sheet through the first movable part. The second protective film has a second sticking part and a second movable part, and the second protective film and the first protective film are separately formed. The second protective film is attached to the first protective film through the second adhesive layer, and the second protective film is removed from the first protective film through the second movable part.
摘要翻译：复合覆盖片包括第一保护膜，第一粘合剂层，第二保护膜和第二粘合剂层。第一保护膜具有第一粘着部和第一可动部。第一保护膜通过第一粘合剂层附着到基片上，并且第一保护膜通过第一可移动部分从基片移除。第二保护膜具有第二粘贴部和第二可动部，第二保护膜和第一保护膜分别形成。第二保护膜通过第二粘合剂层附接到第一保护膜，并且通过第二可移动部分从第一保护膜去除第二保护膜。

23. 发明申请

US20110258555A1 SYSTEMS AND METHODS FOR INTERFACE MANAGEMENT 审中-公开
标题翻译：用于界面管理的系统和方法
公开(公告)号：US20110258555A1
公开(公告)日：2011-10-20
申请号：US13086118
申请日：2011-04-13
申请人： Po-Yen LEE , Pai-Chang Yeh , Chien-Wen Chen , Li-Wen Lian
发明人： Po-Yen LEE , Pai-Chang Yeh , Chien-Wen Chen , Li-Wen Lian
IPC分类号： G06F3/01 , G06F15/16
CPC分类号： G06Q10/00 , G06F9/451
摘要： Methods and systems for interface management are provided. First, a request message, requesting for arrangement information of at least one interface is received from a server, wherein the at least one interface contains at least one object and can be displayed on a screen of an electronic device according to the arrangement information. In response to the request message, respective arrangement information of the at least one interface is obtained and then transmitted to the server, such that a simulated interface of the at least one interface is displayed on a user interface at the server side based on the respective arrangement information received by the server, wherein when a change is made to the simulated interface of the at least one interface at the server side, the arrangement of the at least one interface is accordingly changed.
摘要翻译：提供了接口管理的方法和系统。首先，从服务器接收请求消息至少一个接口的配置信息的请求消息，其中，所述至少一个接口包含至少一个对象，并且可以根据所述配置信息显示在电子设备的屏幕上。响应于请求消息，获得至少一个接口的各自的配置信息，然后发送到服务器，使得至少一个接口的模拟接口基于相应的在服务器侧的用户接口上显示由所述服务器接收的配置信息，其中当对所述服务器侧的所述至少一个接口的所述模拟接口进行改变时，所述至少一个接口的配置相应地改变。

24. 发明申请

US20110023003A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits 有权
标题翻译：超大型集成电路的精确寄生电容提取
公开(公告)号：US20110023003A1
公开(公告)日：2011-01-27
申请号：US12893870
申请日：2010-09-29
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

25. 发明授权

US07818698B2 Accurate parasitic capacitance extraction for ultra large scale integrated circuits 有权
标题翻译：超大规模集成电路的精确寄生电容提取
公开(公告)号：US07818698B2
公开(公告)日：2010-10-19
申请号：US11865304
申请日：2007-10-01
申请人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
发明人： Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G01R31/2853 , G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
摘要翻译：提供了一种用于提取集成电路中的寄生接触/通孔电容的系统和方法。使用该系统的寄生提取可以通过考虑实际的接触/通孔形状和尺寸变化而提高接触/通过寄生电容提取的精度。各种实施例的共同特征包括生成技术文件的步骤，其中电容表中的接触/通孔电容从有效接触/通孔宽度表导出。有效接触/通孔宽度表的每个元件被校准以具有与IC中发生的实际接触/通孔配置的寄生电容匹配的寄生电容。

26. 发明申请

US20080161554A1 Macrocyclic carbodiimides (MC-CDI) and their derivatives, syntheses and applications of the same 失效
标题翻译：大环碳二亚胺（MC-CDI）及其衍生物，合成及应用相同
公开(公告)号：US20080161554A1
公开(公告)日：2008-07-03
申请号：US11646589
申请日：2006-12-28
申请人： Shenghong A. Dai , Chih-Chia Cheng , Chien-Wen Chen , Chih-Hung Chen
发明人： Shenghong A. Dai , Chih-Chia Cheng , Chien-Wen Chen , Chih-Hung Chen
IPC分类号： C07D273/00 , C07D267/22
CPC分类号： C08G18/4825 , C08G18/10 , C08G18/7621 , C08G18/797 , C08G18/025
摘要： Disclosed are a macrocyclic carbodiimide (MC-CDI) and a process for synthesizing the same through condensation of a molecule with multiple-isocyanate terminal functional groups under high dilution in the presence of a phospholene catalyst such as phospholene or arsenic catalyst. Also disclosed are MC-CDI derivatives, such as MC-urea (MC-U), MC-acylurea (MC-ACU), acid functionalized MC-ACU, and anhydride functionalized MC-ACU, processes for synthesizing the same, and the applications of such derivatives as hydrolysis stabilizers in organic polymeric materials, such as polyurethane (PU) and polyesters, as well as the applications in the syntheses of the amide- and imide-modified polyurethane by ring-opening reaction of the MC-ACU.
摘要翻译：公开了一种大环碳二亚胺（MC-CDI）及其通过在磷酸催化剂如磷酰或砷催化剂存在下在高稀释度下通过分子与多异氰酸酯末端官能团的缩合来合成它的方法。还公开了MC-CDI衍生物，例如MC-脲（MC-U），MC-酰基脲（MC-ACU），酸官能化的MC-ACU和酸酐官能化的MC-ACU，其合成方法和应用的有机聚合材料如聚氨酯（PU）和聚酯中的水解稳定剂的衍生物，以及通过MC-ACU的开环反应合成酰胺和酰亚胺改性的聚氨酯的应用。

27. 发明申请

US20060188824A1 Method for improving design window 有权
标题翻译：改善设计窗口的方法
公开(公告)号：US20060188824A1
公开(公告)日：2006-08-24
申请号：US11320513
申请日：2005-12-27
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： G03F7/00
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

28. 发明授权

US06855967B2 Utilization of MACRO power routing area for buffer insertion 有权
标题翻译：利用MACRO电源路由区进行缓冲区插入
公开(公告)号：US06855967B2
公开(公告)日：2005-02-15
申请号：US10283892
申请日：2002-10-30
申请人： Louis Chao-Chiuan Liu , Chien-Wen Chen
发明人： Louis Chao-Chiuan Liu , Chien-Wen Chen
IPC分类号： H01L23/528 , H01L27/10 , H01L23/04 , H01L23/48 , H01L23/52
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.
摘要翻译：用于在宏块区域中的宏小区之间的电力线区域中形成缓冲单元的结构和方法。在电源线电平上，在VSS和VDD线之间形成一个引脚。引脚连接到缓冲单元。接下来，形成信号线层，信号线连接到引脚和驱动器。在第一实施例中，驱动器形成在标准单元区域中。在第二实施例中，驱动器形成在宏小区中。信号线连接到引脚和驱动器。

29. 发明授权

US08543333B2 Method, system, apparatus and computer-readable medium for browsing spot information 有权
标题翻译：用于浏览现场信息的方法，系统，装置和计算机可读介质
公开(公告)号：US08543333B2
公开(公告)日：2013-09-24
申请号：US13039314
申请日：2011-03-03
申请人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
发明人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
IPC分类号： G01C21/00 , G08G1/123
CPC分类号： G06F3/04842 , G01C21/00 , G01C21/3682 , G09B29/007
摘要： A method, a system, an apparatus, and a computer-readable medium for browsing spot information, adapted to an electronic device, are provided. In the present method, a plurality of spot information are retrieved, in which each of the spot information at least comprises a picture and a location of a spot. Next, an electronic map is displayed and a spot marker is marked at the spot location of each spot information on the electronic map. Meanwhile, a spot browsing bar is displayed on a side of the electronic map and the spot pictures of the spot information are sequentially displayed in the spot browsing bar. When a select operation of a certain spot marker on the electronic map is received, the spot browsing bar is scrolled to show the spot picture corresponding to the selected spot marker.
摘要翻译：提供了适用于电子设备的用于浏览点信息的方法，系统，装置和计算机可读介质。在本方法中，检索多个点信息，其中每个点信息至少包括图片和点的位置。接下来，显示电子地图，并且在电子地图上的每个点信息的点位置处标记点标记。同时，在电子地图的一侧显示现场浏览栏，并且在点浏览栏中顺序地显示点信息的照片。当接收到电子地图上的特定点标记的选择操作时，滚动显示浏览栏以显示与所选择的点标记对应的点图。

30. 发明授权

US08518722B2 Method for detecting the under-fill void in flip chip BGA 有权
标题翻译：用于检测倒装芯片BGA中欠补充空隙的方法
公开(公告)号：US08518722B2
公开(公告)日：2013-08-27
申请号：US13064161
申请日：2011-03-09
申请人： Chien-Wen Chen , Chia-Jen Kao , Jui-Cheng Chuang
发明人： Chien-Wen Chen , Chia-Jen Kao , Jui-Cheng Chuang
IPC分类号： H01L21/66
CPC分类号： H01L23/49816 , H01L21/563 , H01L22/12 , H01L23/055 , H01L23/49827 , H01L24/81 , H01L2224/16235 , H01L2224/16238 , H01L2224/8123 , H01L2224/81815 , H01L2224/81908 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01074 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00
摘要： A method for detecting the under-fill void of the flip chip ball grid array package structure is provided, which includes providing a substrate having an interconnect structure and a plurality of interposers therein; providing a chip having an active surface and a back side, and a plurality of first connecting elements on the active surface of the chip; mounting and electrically connecting the active surface of the chip on the substrate; performing at least once IR reflow to fix the plurality of first connecting elements on the substrate; filling an encapsulate material to cover the active surface of the chip and the plurality of first connecting elements; performing a detecting process to detect that void is not formed between the active surface of the chip and the plurality of first elements; and forming a plurality of second connecting elements on the back side of the substrate to obtain a flip chip ball grid array package structure.
摘要翻译：提供了一种用于检测倒装芯片球栅阵列封装结构的欠补充空隙的方法，其包括在其中提供具有互连结构的衬底和多个中介层; 提供具有活性表面和背面的芯片，以及在芯片的有源表面上的多个第一连接元件; 将所述芯片的有源表面安装并电连接在所述基板上; 执行至少一次IR回流以将所述多个第一连接元件固定在所述基板上; 填充封装材料以覆盖所述芯片的有效表面和所述多个第一连接元件; 执行检测处理以检测在所述芯片的有效表面和所述多个第一元件之间不形成所述空隙; 以及在所述基板的背面上形成多个第二连接元件以获得倒装芯片球栅阵列封装结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式