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21. 发明授权

US08327243B1 System and method for generating locator polynomials 有权
标题翻译：用于生成定位多项式的系统和方法
公开(公告)号：US08327243B1
公开(公告)日：2012-12-04
申请号：US12857391
申请日：2010-08-16
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： H03M13/00
CPC分类号： H03M13/1525 , H03M13/152
摘要： A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the syndrome sequencer outputs each syndrome of the sequence of syndromes in sequential order. The sequential polynomial generator generates a locator polynomial in a number of iterations based on the sequence of syndromes received from the syndrome sequencer.
摘要翻译：综合征发生器产生一系列综合征的奇异综合征，并将奇数综合征存储在寄存器中。一个综合征定序器识别存储综合征序列的下一个综合征的寄存器，从该寄存器中读取该综合征，并将这个综合征输出到一个顺序多项式发生器。此外，综合征序列发生器通过平方从寄存器读取的综合征产生均匀综合征，并将均匀综合征写入同一寄存器。此外，综合征序列分析器按顺序输出综合征序列的每个综合征。顺序多项式生成器基于从综合征序列器接收到的综合征序列，在多次迭代中产生定位多项式。

22. 发明授权

US08285884B1 Data aggregation system and method for deskewing data at selectable data rates 有权
标题翻译：用于以可选数据速率对数据进行偏移的数据汇总系统和方法
公开(公告)号：US08285884B1
公开(公告)日：2012-10-09
申请号：US12264184
申请日：2008-11-03
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： G06F3/00 , G06F1/04
CPC分类号： G06F13/4278 , Y02D10/14 , Y02D10/151
摘要： A deskew module of a receiver includes deskew units, each of which includes a data aggregation module for selecting a data rate for receiving symbols of a corresponding data stream. The deskew unit includes a data aggregation module that aggregates a predetermined number of the symbols in one or more clock cycles of a clock signal based on the data rate. The predetermined number of symbols is the same for each data rate selectable by the data aggregation module. The data aggregation module outputs the aggregated symbols to a deskew buffer of the deskew unit in a clock cycle of a clock signal. The deskew buffer deskews symbols received from the data aggregation module and outputs the deskewed symbols.
摘要翻译：接收机的去歪斜模块包括歪斜偏移单元，每个单元包括用于选择用于接收对应数据流的符号的数据速率的数据聚合模块。该偏斜校正单元包括数据聚合模块，其基于数据速率在时钟信号的一个或多个时钟周期中聚合预定数量的符号。对于由数据聚合模块选择的每个数据速率，预定数量的符号是相同的。数据聚合模块以时钟信号的时钟周期将聚合符号输出到偏移校正单元的偏移缓冲器。偏移校正缓冲器偏移从数据聚合模块接收到的符号，并输出偏斜校正的符号。

23. 发明授权

US08161210B1 Multi-queue system and method for deskewing symbols in data streams 有权
标题翻译：用于数据流中的符号的偏移校正的多队列系统和方法
公开(公告)号：US08161210B1
公开(公告)日：2012-04-17
申请号：US12264158
申请日：2008-11-03
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： G06F3/03
CPC分类号： H04L25/14
摘要： A communication system includes a transmitter that transmits multiple data streams to a receiver in the communication system. Each of the data streams includes data and a skip ordered set. The receiver includes a deskew unit for each data stream, each of which includes multiple data queues. Each of the deskew units stores symbols of the data stream received by the deskew unit into the data queues of the data unit by distributing the symbols among the data queues. The deskew unit aligns data symbols across the data streams by deskewing symbols stored in the data queues of the deskew units based on skip ordered sets in the deskew units. Moreover, the receiver may deskew more than one symbol per clock cycle.
摘要翻译：通信系统包括向通信系统中的接收机发送多个数据流的发射机。每个数据流包括数据和跳过有序集。接收机包括用于每个数据流的歪斜单元，每个数据流包括多个数据队列。每个偏斜校正单元通过在数据队列之间分配符号来将由偏斜校正单元接收的数据流的符号存储到数据单元的数据队列中。该偏斜校正单元通过基于在去歪斜单位中的跳过有序集合对存在于歪斜扫描单元的数据队列中的符号进行偏移校正来跨数据流对准数据符号。而且，每个时钟周期，接收机可能会偏移多于一个符号。

24. 发明授权

US07694025B1 Method and device for base address sorting and entry into base address registers 有权
标题翻译：用于基地址排序和进入基地址寄存器的方法和设备
公开(公告)号：US07694025B1
公开(公告)日：2010-04-06
申请号：US11395918
申请日：2006-03-31
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： G06F3/00
CPC分类号： G06F3/007 , G06F3/00
摘要： A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.
摘要翻译：公开了一种串行开关中的基址分类装置，其包括一组影子寄存器，阵列中的每个阴影寄存器电耦合到基地址寄存器，基地址寄存器阵列中，每个基址寄存器具有基地址和控制逻辑电路，电耦合到影子寄存器阵列和基地址寄存器阵列，当控制逻辑电路接收到配置命令时，可实现一种方法，用于重新配置阵列的内容的基地址寄存器，包括：将新的基地址从配置命令插入到影子寄存器阵列中的影子寄存器中，将影子寄存器阵列按预定顺序排序，然后将影子寄存器阵列的内容复制到基地址寄存器阵列。

25. 发明授权

US06311298B1 Mechanism to simplify built-in self test of a control store unit 失效
标题翻译：简化控制存储单元内置自检的机制
公开(公告)号：US06311298B1
公开(公告)日：2001-10-30
申请号：US09251788
申请日：1999-02-17
申请人： Christopher I. W. Norrie
发明人： Christopher I. W. Norrie
IPC分类号： G11C2900
CPC分类号： G11C29/20 , G11C29/10 , G11C29/32 , G11C29/46
摘要： A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In response to a test enable signal, the address generator switches between two modes: a normal mode and a test mode. Under the normal mode, normal control store addresses are generated. Under the test mode, a sequence of BIST/logout addresses are generated that sequentially cycles through the entire control store memory at full CPU speed.
摘要翻译：控制存储单元，其具有能够提供正常控制存储地址生成功能和BIST /注销地址生成功能的控制存储地址生成器。响应于测试使能信号，地址发生器在两种模式之间切换：正常模式和测试模式。在正常模式下，生成正常的控制存储地址。在测试模式下，生成一系列BIST /注销地址，以完整的CPU速度顺序循环整个控制存储器。

26. 发明授权

US5408674A System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size 失效
标题翻译：用于通过将两个字节的操作码映射到控制存储器中以检查两字节操作码的有效性的系统，以减少存储器大小
公开(公告)号：US5408674A
公开(公告)日：1995-04-18
申请号：US995772
申请日：1992-12-23
申请人： Christopher I. W. Norrie , Carolee N. Newcomb , Peter K. Yu
发明人： Christopher I. W. Norrie , Carolee N. Newcomb , Peter K. Yu
IPC分类号： G06F9/30 , G06F9/32 , G06F9/28
CPC分类号： G06F9/30145
摘要： A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies that specific operation code within the identified series, the mapping system comprising a first register for storing the first and second bytes of a two byte operation codes, a first control store for storing control word for the two byte operation codes, a first means for generating, from the first and second bytes stored in the first register, a first control store address for the first control store thereby providing access to the control word for processing the two byte operation code store in the first register and a second means for generating, from the first and second bytes stored in the first register, a first signal when an invalid two byte operation code has been stored in the first register for processing, the first signal invalidating the processing of the two byte operation code stored in the first register including any processing of the control word accessed by the first control store in response to the first control store address generated by the first means.
摘要翻译：一种用于将多个两字节操作代码序列映射到控制存储器中的映射系统，其中在每个两字节操作代码中，第一字节标识包含该两字节操作代码的序列，而第二字节标识该字节内的特定操作码所述映射系统包括用于存储两字节操作码的第一和第二字节的第一寄存器，用于存储用于所述两字节操作码的控制字的第一控制存储器，用于从所述第一和第二字节存储在第一寄存器中的字节，用于第一控制存储器的第一控制存储地址，从而提供对用于处理第一寄存器中的两字节操作代码存储的控制字的访问;以及第二装置，用于从存储的第一和第二字节在第一个寄存器中，第一个信号当一个无效的两个字节的操作码已被存储在第一个寄存器中进行处理时，第一个信号进入验证存储在第一寄存器中的两字节操作码的处理，包括响应于由第一装置产生的第一控制存储地址由第一控制存储器访问的控制字的任何处理。

27. 发明授权

US5386549A Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture 失效
标题翻译：用于恢复在采用管道架构的计算机系统中的控制存储中发生的错误的错误恢复系统
公开(公告)号：US5386549A
公开(公告)日：1995-01-31
申请号：US978829
申请日：1992-11-19
申请人： Christopher I. W. Norrie , Carolee V. Newcomb , Peter K. Yu , Allan Zmyslowski
发明人： Christopher I. W. Norrie , Carolee V. Newcomb , Peter K. Yu , Allan Zmyslowski
IPC分类号： G06F11/00 , G06F11/10 , H03M13/00
CPC分类号： G06F11/1666 , G06F11/1008 , G06F11/1076 , G06F11/1405
摘要： An error recovery system used in a pipeline architecture type computer system for recovering from an error in a control word for an instruction without interrupting the sequence of processing control words by the computer system. The computer system processes instructions in a sequence of overlapping FLOWs where each FLOW is comprised of a sequence of cycles. An instruction control word is processed in each cycle of each FLOW. The error recovery system comprises a first storage for storing, for a given cycle of a FLOW, all the control words for all the instructions, a second storage for storing a control word read from the first storage and an error recovery logic for detecting an error in the control word read from the first storage and stored in the second storage and for correcting the error in the control word in the first and second storage.
摘要翻译：一种在流水线架构型计算机系统中使用的错误恢复系统，用于从指令的控制字中的错误中恢复，而不会中断计算机系统处理控制字的序列。计算机系统处理重叠FLOW序列中的指令，其中每个FLOW由循环序列组成。在每个流程的每个循环中处理指令控制字。错误恢复系统包括第一存储器，用于在FLOW的给定周期中存储用于所有指令的所有控制字，用于存储从第一存储器读取的控制字的第二存储器和用于检测错误的错误恢复逻辑在从第一存储器读取并存储在第二存储器中的控制字中，并用于校正第一和第二存储器中的控制字中的错误。

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