专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20050124107A1 Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device 失效
标题翻译：制造具有沟槽隔离结构和半导体器件的半导体器件的方法
公开(公告)号：US20050124107A1
公开(公告)日：2005-06-09
申请号：US11033322
申请日：2005-01-12
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译：本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

22. 发明授权

US08853663B2 Nonvolatile memory device and manufacturing method thereof 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08853663B2
公开(公告)日：2014-10-07
申请号：US13252690
申请日：2011-10-04
申请人： Jun Sumino
发明人： Jun Sumino
IPC分类号： H01L21/8239 , H01L45/00 , G11C13/00
CPC分类号： H01L45/144 , G11C13/0002 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1286 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A nonvolatile memory device is disclosed, in which a first electrode, a first material layer having a positive Peltier coefficient, an information storage layer, a second material layer having a negative Peltier coefficient, and a second electrode are laminated.
摘要翻译：公开了一种非易失性存储器件，其中层压有第一电极，具有正珀尔帖系数的第一材料层，信息存储层，具有负珀尔帖系数的第二材料层和第二电极。

23. 发明授权

US08687404B2 Memory element and drive method for the same, and memory device 有权
标题翻译：存储器元件和驱动方法相同，和存储器件
公开(公告)号：US08687404B2
公开(公告)日：2014-04-01
申请号：US13164945
申请日：2011-06-21
申请人： Masayuki Shimuta , Jun Sumino , Shuichiro Yasuda
发明人： Masayuki Shimuta , Jun Sumino , Shuichiro Yasuda
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C2213/75 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/144 , H01L45/146
摘要： A memory element capable of increasing capacity with an improvement of distribution of resistance in the high-resistance state, a drive method therefor, and a memory device are provided. The memory element includes first and second electrodes, and a plurality of resistance change elements electrically connected in series between the first and second electrodes, whose resistance values are reversibly changeable in response to application of a voltage to the first and second electrodes, and changeable to the same resistance state relative to the voltage application.
摘要翻译：提供了能够通过改善高电阻状态下的电阻分布来提高容量的存储元件，其驱动方法和存储器件。存储元件包括第一和第二电极以及串联电连接在第一和第二电极之间的多个电阻变化元件，其电阻值可响应于向第一和第二电极施加电压而可逆地改变，并且可改变为相对于电压施加相同的电阻状态。

24. 发明授权

US07694066B2 Nonvolatile memory with active and passive wear leveling 有权
标题翻译：具有主动和被动磨损均衡的非易失性存储器
公开(公告)号：US07694066B2
公开(公告)日：2010-04-06
申请号：US11594082
申请日：2006-11-08
申请人： Koji Sakui , Kazuhiro Suzuki , Daisuke Yoshioka , Kazuto Kamimura , Takeshi Ishimoto , Jun Sumino
发明人： Koji Sakui , Kazuhiro Suzuki , Daisuke Yoshioka , Kazuto Kamimura , Takeshi Ishimoto , Jun Sumino
IPC分类号： G06F13/00
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/3495
摘要： A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.
摘要翻译：包括非易失性半导体存储装置的存储器系统包括：非易失性存储单元，其包括数据被频繁地重写的第一数据区域和几乎不被重写数据的第二数据区域; 和控制单元。控制单元依次选择数据难以重写的第二数据区域中的逻辑块地址，并将数据被频繁重写的第一数据区域中的新的重写目的地的物理块地址更新为与所选择的逻辑块地址相对应的物理块地址。

25. 发明申请

US20070269949A1 Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 有权
标题翻译：制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法
公开(公告)号：US20070269949A1
公开(公告)日：2007-11-22
申请号：US11822467
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译：本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

26. 发明申请

US20050275063A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20050275063A1
公开(公告)日：2005-12-15
申请号：US10617667
申请日：2003-07-14
申请人： Jun Sumino , Satoshi Shimizu
发明人： Jun Sumino , Satoshi Shimizu
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/76232 , H01L21/76235 , H01L27/115
摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.
摘要翻译：半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

27. 发明授权

US6153493A Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US6153493A
公开(公告)日：2000-11-28
申请号：US116880
申请日：1998-07-16
申请人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
发明人： Hiromi Makimoto , Moriyoshi Nakashima , Kojiro Yuzuriha , Makoto Ooi , Jun Sumino
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.
摘要翻译：形成精细且具有较小的鸟头动作的场氧化膜，从而改善形成在位于场氧化膜上的端部的导电层的电特性。在氮化硅膜和热氧化膜上形成平坦化硅膜，以平坦化在热氧化膜和氮化硅膜之间产生的凹。平坦化硅膜被热氧化，以形成与热氧化膜一体化的平坦化热氧化膜。此后，平面化热氧化膜被回蚀以形成场氧化物膜，并且去除氮化硅膜和多晶硅膜。此后，形成具有位于场氧化膜上的端部的导电层。

28. 发明申请

US20120091423A1 NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120091423A1
公开(公告)日：2012-04-19
申请号：US13252690
申请日：2011-10-04
申请人： Jun Sumino
发明人： Jun Sumino
IPC分类号： H01L47/00 , H01L21/8239
CPC分类号： H01L45/144 , G11C13/0002 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1286 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A nonvolatile memory device is disclosed, in which a first electrode, a first material layer having a positive Peltier coefficient, an information storage layer, a second material layer having a negative Peltier coefficient, and a second electrode are laminated.
摘要翻译：公开了一种非易失性存储器件，其中层压有第一电极，具有正珀尔帖系数的第一材料层，信息存储层，具有负珀尔帖系数的第二材料层和第二电极。

29. 发明申请

US20080017903A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A TRENCH ISOLATION STRUCTURE AND RESULTING SEMICONDUCTOR DEVICE 失效
标题翻译：制造具有耐热隔离结构和半导体器件的半导体器件的方法
公开(公告)号：US20080017903A1
公开(公告)日：2008-01-24
申请号：US11822470
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L31/119
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译：本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

30. 发明申请

US20070103992A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070103992A1
公开(公告)日：2007-05-10
申请号：US11594082
申请日：2006-11-08
申请人： Koji Sakui , Kazuhiro Suzuki , Daisuke Yoshioka , Kazuto Kamimura , Takeshi Ishimoto , Jun Sumino
发明人： Koji Sakui , Kazuhiro Suzuki , Daisuke Yoshioka , Kazuto Kamimura , Takeshi Ishimoto , Jun Sumino
IPC分类号： G11C16/04 , G06F12/00
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/3495
摘要： A memory system including a nonvolatile semiconductor storage device includes: a nonvolatile memory unit that includes a first data area in which data is frequently rewritten and a second data area in which data is hardly rewritten; and a control unit. The control unit sequentially selects logical block addresses in the second data area in which data is hardly rewritten and updates physical block addresses at new rewriting destinations in the first data area in which data is frequently rewritten to physical block addresses corresponding to the logical block addresses selected.
摘要翻译：包括非易失性半导体存储装置的存储器系统包括：非易失性存储单元，其包括数据被频繁地重写的第一数据区域和几乎不被重写数据的第二数据区域; 和控制单元。控制单元依次选择数据难以重写的第二数据区域中的逻辑块地址，并将数据被频繁重写的第一数据区域中的新的重写目的地的物理块地址更新为与所选择的逻辑块地址相对应的物理块地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式