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21. 发明授权

US07873925B2 Method and apparatus for computing test margins for at-speed testing 有权
标题翻译：用于计算速度测试的测试余量的方法和装置
公开(公告)号：US07873925B2
公开(公告)日：2011-01-18
申请号：US12013925
申请日：2008-01-14
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725
摘要： In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.
摘要翻译：在一个实施例中，本发明是用于计算集成电路芯片的高速测试的裕量的方法和装置。用于计算集成电路芯片设计的高速测试的余量的方法的一个实施例包括计算芯片的统计芯片松弛，计算芯片的统计测试松弛，以及从芯片松弛和测试中计算余量松弛。

22. 发明申请

US20130283223A1 ENABLING STATISTICAL TESTING USING DETERMINISTIC MULTI-CORNER TIMING ANALYSIS 失效
标题翻译：使用决定性多角度时序分析实现统计测试
公开(公告)号：US20130283223A1
公开(公告)日：2013-10-24
申请号：US13454795
申请日：2012-04-24
申请人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
发明人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.
摘要翻译：在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。

23. 发明申请

US20130014075A1 DESIGN-DEPENDENT INTEGRATED CIRCUIT DISPOSITION 有权
标题翻译：设计相关集成电路处理
公开(公告)号：US20130014075A1
公开(公告)日：2013-01-10
申请号：US13617749
申请日：2012-09-14
申请人： Peter Anton Habitz , Jinjun Xiong , Vladimir Zolotov
发明人： Peter Anton Habitz , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.
摘要翻译：集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。

24. 发明申请

US20120191401A1 METHOD AND APPARATUS FOR GENERATING TEST PATTERNS FOR USE IN AT-SPEED TESTING 有权
标题翻译：用于产生用于速度测试的测试模式的方法和装置
公开(公告)号：US20120191401A1
公开(公告)日：2012-07-26
申请号：US13439188
申请日：2012-04-04
申请人： CHANDRAMOULI VISWESWARIAH , Jinjun Xiong , Vladimir Zolotov
发明人： CHANDRAMOULI VISWESWARIAH , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F19/00
CPC分类号： G01R31/318328 , G01R31/318342
摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.
摘要翻译：在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径一套测试模式。

25. 发明申请

US20120124535A1 Optimal Chip Acceptance Criterion and its Applications 失效
标题翻译：最佳芯片验收标准及其应用
公开(公告)号：US20120124535A1
公开(公告)日：2012-05-17
申请号：US12946950
申请日：2010-11-16
申请人： Jinjun Xiong , Vladimir Zolotov
发明人： Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31718
摘要： At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.
摘要翻译：针对要优化制造芯片测试的集成电路芯片设计识别至少一个目标度量。还针对要优化制造芯片测试的集成电路芯片设计识别至少一个替代度量。使用一般联合概率密度函数来建模所述至少一个目标度量和所述至少一个代理度量之间的关系。基于通用联合概率密度函数确定芯片配置准则。芯片配置标准对于根据设计推定制造的给定物理芯片，基于给定物理芯片的至少一个替代度量来确定在制造芯片测试期间是否接受或丢弃给定的物理芯片。

26. 发明授权

US08176462B2 Method and apparatus for generating test patterns for use in at-speed testing 有权
标题翻译：用于生成用于速度测试的测试模式的方法和装置
公开(公告)号：US08176462B2
公开(公告)日：2012-05-08
申请号：US12464025
申请日：2009-05-11
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F11/22 , G06F17/50
CPC分类号： G01R31/318328 , G01R31/318342
摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.
摘要翻译：在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径一套测试模式。

27. 发明申请

US20100162064A1 METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING 有权
标题翻译：用于在速度测试期间覆盖多层过程空间的方法和装置
公开(公告)号：US20100162064A1
公开(公告)日：2010-06-24
申请号：US12340072
申请日：2008-12-19
申请人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882
摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
摘要翻译：在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试将会失败，计算基本上确保路径组满足N和M要求并输出用于选择路径集合的度量的度量。

28. 发明授权

US07480880B2 Method, system, and program product for computing a yield gradient from statistical timing 有权
标题翻译：用于从统计时序计算产量梯度的方法，系统和程序产品
公开(公告)号：US07480880B2
公开(公告)日：2009-01-20
申请号：US11358622
申请日：2006-02-21
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/509 , G06F17/5031 , G06F17/504 , G06F2217/10 , G06F2217/12 , Y02P90/265
摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.
摘要翻译：本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：执行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。

29. 发明授权

US08781792B2 Yield computation and optimization for selective voltage binning 有权
标题翻译：选择性电压合并的产量计算和优化
公开(公告)号：US08781792B2
公开(公告)日：2014-07-15
申请号：US12610291
申请日：2009-10-31
申请人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译：提供了用于提高制造芯片的参数芯片产量的技术。在一方面，提供了一种用于优化参数芯片产量的方法。该方法包括以下步骤。基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。然后确定计算的参数芯片产量是否是最佳的。如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。否则，binning方案保持不变。

30. 发明授权

US08560994B1 Enabling statistical testing using deterministic multi-corner timing analysis 失效
标题翻译：使用确定性多角时序分析实现统计测试
公开(公告)号：US08560994B1
公开(公告)日：2013-10-15
申请号：US13454795
申请日：2012-04-24
申请人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
发明人： Bhavna Agrawal , David S. Kung , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G01R31/31725 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.
摘要翻译：在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。

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