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21. 发明授权

US06486518B1 Structures and method with bitline self-aligned to vertical connection 有权
标题翻译：具有位线自对准到垂直连接的结构和方法
公开(公告)号：US06486518B1
公开(公告)日：2002-11-26
申请号：US09407420
申请日：1999-09-29
申请人： Yasuhiro Okumoto , Michio Nishimura , Toshiyuki Nagata
发明人： Yasuhiro Okumoto , Michio Nishimura , Toshiyuki Nagata
IPC分类号： H01L27108
CPC分类号： H01L27/10814 , H01L21/76897 , H01L27/10855 , H01L27/10885
摘要： A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.
摘要翻译：将金属位线与位线上的电容器垂直互连的方法。在这类实施例中，垂直互连支柱是在完成位线的制造之前形成的。为了实现这一点，使用允许其沿着垂直互连柱的壁垂直延伸但不在位线金属和垂直互连柱之间形成任何电连接的台阶来对位线金属进行图案化。

22. 发明授权

US06381166B1 Semiconductor memory device having variable pitch array 有权
标题翻译：具有可变间距阵列的半导体存储器件
公开(公告)号：US06381166B1
公开(公告)日：2002-04-30
申请号：US09399841
申请日：1999-09-21
申请人： Hiroyuki Yoshida , Toshiyuki Nagata , Atsushi Satoh , Shuzoh Shiosaki
发明人： Hiroyuki Yoshida , Toshiyuki Nagata , Atsushi Satoh , Shuzoh Shiosaki
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： A memory cell array (300) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines (302a) having a first pitch, and peripheral word lines (302b), situated proximate to the edge of the array (300), having a second pitch that is greater than the first pitch. In a similar fashion, the bit lines include central bit lines (304a) having a third pitch, and peripheral bit lines (304b), situated proximate to the edge of the array (300), having a fourth pitch that is greater than the third pitch. The increase in word line and bit line pitch can reduce the adverse results of proximity effects caused by the junction of the dense array features with the relatively open features of the adjacent periphery circuits.
摘要翻译：公开了一种具有可变间距字线和位线的存储单元阵列（300）。字线包括具有第一间距的中心字线（302a）和位于阵列（300）的边缘附近的外围字线（302b），具有大于第一间距的第二间距。以类似的方式，位线包括具有第三间距的中心位线（304a）和位于阵列（300）的边缘附近的周边位线（304b），其具有大于第三间距的第三间距沥青。字线和位线间距的增加可以减少密集阵列特征与相邻外围电路的相对开放特征的接合引起的邻近效应的不良结果。

23. 发明授权

US06291293B1 Method for fabricating an open can-type stacked capacitor on an uneven surface 有权
标题翻译：在不平坦表面上制造开罐式叠层电容器的方法
公开(公告)号：US06291293B1
公开(公告)日：2001-09-18
申请号：US09373484
申请日：1999-08-12
申请人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
发明人： Yoichi Miyai , Masayuki Moroi , Katsushi Boku , Toshiyuki Nagata
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L28/92
摘要： An open can-type stacked capacitor is fabricated by forming a conductive layer (30, 130) outwardly of a substantially uneven surface (12, 112). A step (50, 150) is formed in an outer surface (32, 132) of the conductive layer (30, 130). A base (72, 172, 202) of a first electrode (70, 170, 200) is formed by removing a predetermined thickness (66, 166) of at least part of the conductive layer (30, 130). The base (72, 172, 202) is made of a portion of the conductive layer (30, 130) underlying the step (50, 150) by the predetermined thickness (66, 166). A sidewall (74, 174) of the first electrode (70, 170, 200) is formed. A dielectric layer (80) is formed outwardly of the first electrode (70, 170, 200). A second electrode (82) of the capacitor is formed outwardly of the dielectric layer (80).
摘要翻译：通过在基本上不平坦的表面（12,112）外部形成导电层（30,130）来制造开放式罐式叠层电容器。在导电层（30,130）的外表面（32,132）中形成台阶（50,150）。通过去除导电层（30,130）的至少一部分的预定厚度（66,166）来形成第一电极（70,170,200）的基底（72,172,202）。基座（72,172,202）由位于台阶（50,150）下方的预定厚度（66,166）的导电层（30,130）的一部分制成。第一电极（70,170,200）的侧壁（74,174）形成。介电层（80）形成在第一电极（70,170,200）的外侧。电容器的第二电极（82）形成在电介质层（80）的外侧。

24. 发明授权

US6166941A Relaxed layout for storage nodes for dynamic random access memories 有权
标题翻译：用于动态随机存取存储器的存储节点的宽松布局
公开(公告)号：US6166941A
公开(公告)日：2000-12-26
申请号：US329664
申请日：1999-06-10
申请人： Hiroyuki Yoshida , Toshiyuki Nagata
发明人： Hiroyuki Yoshida , Toshiyuki Nagata
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , G11C5/02
CPC分类号： H01L27/10808
摘要： A memory cell structure (10) includes a plurality of bit lines (12) and intersecting word lines (14). Bit line contacts (16) are spaced evenly apart on an associated bit line (12). A plurality of storage nodes (20) and associated storage node contacts (18) are provided. Storage nodes (20) and storage node contacts (2) are spaced evenly apart along the associated bit line (12). The storage nodes (20) and storage node contacts (18) are offset with respect to storage nodes (20) and storage node contacts (18) placed along adjacent bit lines (12).
摘要翻译：存储单元结构（10）包括多个位线（12）和相交字线（14）。位线触点（16）在相关位线（12）上均匀间隔开。提供了多个存储节点（20）和相关联的存储节点触点（18）。存储节点（20）和存储节点触点（2）沿相关联的位线（12）间隔开间隔开。存储节点（20）和存储节点触点（18）相对于沿相邻位线（12）放置的存储节点（20）和存储节点触点（18）偏移。

25. 发明授权

US5861649A Trench-type semiconductor memory device 失效
标题翻译：沟槽型半导体存储器件
公开(公告)号：US5861649A
公开(公告)日：1999-01-19
申请号：US871530
申请日：1992-04-21
申请人： Hiroyuki Yoshida , Takayuki Niuya , Toshiyuki Nagata , Yoichi Miyai , Yoshihiro Ogata
发明人： Hiroyuki Yoshida , Takayuki Niuya , Toshiyuki Nagata , Yoichi Miyai , Yoshihiro Ogata
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/92 , H01L29/76
CPC分类号： H01L27/10861 , H01L27/10829 , H01L28/40
摘要： A dynamic RAM in which a groove (20) is formed on the main surface of a semiconductor substrate; a highly concentrated semiconductor layer (80) having one conductive type is formed inside the groove (20) to a depth sufficient to contain the first and second impurity diffusion areas (53) and (22), which are formed on the top of this groove and have the opposite conductive type; a capacitor C.sub.1 formed inside the groove (20), while a transfer gate Tr.sub.1 is formed on the highly concentrated semiconductor layer (80); and the diffusion area (53) is used to connect them.
摘要翻译：一种动态RAM，其中在半导体衬底的主表面上形成有沟槽（20）; 在凹槽（20）的内部形成有一个具有一种导电类型的高度集中的半导体层（80），其深度足以容纳形成在该槽的顶部上的第一和第二杂质扩散区域（53）和（22）并具有相反的导电类型; 形成在所述槽（20）内部的电容器C1，同时在所述高度集中的半导体层（80）上形成传输门Tr1。并且扩散区域（53）用于连接它们。

26. 发明授权

US5470778A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5470778A
公开(公告)日：1995-11-28
申请号：US251866
申请日：1994-05-31
申请人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
发明人： Toshiyuki Nagata , Hiroyuki Yoshida , Takayuki Niuya , Yoshihiro Ogata , Katsushi Boku , Yoichi Miyai
IPC分类号： H01L21/205 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).
摘要翻译：一种半导体器件，其中沟槽形沟槽（20）和凹陷（100）形成为在半导体衬底的一侧上是连续的其中上述凹槽和上述凹陷掩埋有多晶硅导电层（103），其导电层的顶部被转换成绝缘体（102），其绝缘膜（102）的底部包含在凹陷（100）中，。

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