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21. 发明申请

US20130009230A1 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE 有权
标题翻译：关键尺寸的优化和基板上及以上图案特征的优化
公开(公告)号：US20130009230A1
公开(公告)日：2013-01-10
申请号：US13613956
申请日：2012-09-13
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L27/088 , H01L27/02
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

22. 发明授权

US08283706B2 Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
标题翻译：优化衬底中和图案上的图案特征的临界尺寸和间距
公开(公告)号：US08283706B2
公开(公告)日：2012-10-09
申请号：US12136766
申请日：2008-06-10
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L29/80
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

23. 发明授权

US08208282B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US08208282B2
公开(公告)日：2012-06-26
申请号：US12899634
申请日：2010-10-07
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/36
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括第一导体，第二导体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。还提供其他方面。

24. 发明申请

US20110019467A1 VERTICALLY STACKED FIELD PROGRAMMABLE NONVOLATILE MEMORY AND METHOD OF FABRICATION 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US20110019467A1
公开(公告)日：2011-01-27
申请号：US12899634
申请日：2010-10-07
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C11/00
CPC分类号： G11C17/06 , G11C11/5692 , G11C13/003 , G11C17/14 , G11C17/16 , G11C17/165 , G11C2213/71 , G11C2213/76 , H01L27/101 , H01L27/1021 , H01L27/2481 , H01L45/1233 , H01L45/16
摘要： A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.
摘要翻译：提供了一种存储单元，其包括第一导体，第二导体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。还提供其他方面。

25. 发明授权

US06881994B2 Monolithic three dimensional array of charge storage devices containing a planarized surface 有权
标题翻译：包含平坦化表面的电荷存储装置的单片三维阵列
公开(公告)号：US06881994B2
公开(公告)日：2005-04-19
申请号：US09927648
申请日：2001-08-13
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L21/20 , H01L21/336 , H01L21/822 , H01L21/8246 , H01L21/8247 , H01L27/06 , H01L27/10 , H01L27/112 , H01L27/12 , H01L29/423 , H01L29/786 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/8242
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

26. 发明授权

US06185122B2 Vertically stacked field programmable nonvolatile memory and method of fabrication 有权
标题翻译：垂直堆叠现场可编程非易失性存储器和制造方法
公开(公告)号：US06185122B2
公开(公告)日：2001-02-06
申请号：US09469658
申请日：1999-12-22
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , P. Michael Farmwald , James M. Cleeves
IPC分类号： G11C1700
CPC分类号： H01L27/1021 , G11C11/5678 , G11C11/5692 , G11C13/003 , G11C17/16 , G11C2213/71 , G11C2213/76
摘要： A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
摘要翻译：公开了一种非常高密度的现场可编程存储器。阵列垂直地形成在衬底上方，使用几层，其各层包括垂直制造的存储单元。 N级阵列中的单元可以形成N + 1掩蔽步骤以及接触所需的掩蔽步骤。自动对准技术的最大限度地使光刻限制最小化。在一个实施例中，外围电路形成在硅衬底中，并且在衬底上方制造N电平阵列。

27. 发明授权

US08981457B2 Dense arrays and charge storage devices 有权
公开(公告)号：US08981457B2
公开(公告)日：2015-03-17
申请号：US13468731
申请日：2012-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Mark G. Johnson , Paul Michael Farmwald , Igor G. Kouznetzov
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Mark G. Johnson , Paul Michael Farmwald , Igor G. Kouznetzov
IPC分类号： H01L29/788 , H01L27/115 , G11C16/34 , H01L21/822 , H01L27/06 , H01L27/112 , H01L29/423 , H01L29/66 , H01L29/792 , H01L29/861 , H01L27/12
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

28. 发明授权

US07825455B2 Three terminal nonvolatile memory device with vertical gated diode 有权
标题翻译：具有垂直门控二极管的三端子非易失性存储器件
公开(公告)号：US07825455B2
公开(公告)日：2010-11-02
申请号：US12320351
申请日：2009-01-23
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Mark G. Johnson , Paul M. Farmwald , Igor G. Kouznetsov
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Mark G. Johnson , Paul M. Farmwald , Igor G. Kouznetsov
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

29. 发明申请

US20090173985A1 Dense arrays and charge storage devices 有权
标题翻译：密集阵列和电荷存储设备
公开(公告)号：US20090173985A1
公开(公告)日：2009-07-09
申请号：US12320351
申请日：2009-01-23
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Peti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Peti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald
IPC分类号： H01L29/792 , H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

30. 发明授权

US06385074B1 Integrated circuit structure including three-dimensional memory array 有权
标题翻译：集成电路结构包括三维存储阵列
公开(公告)号：US06385074B1
公开(公告)日：2002-05-07
申请号：US09748816
申请日：2000-12-22
申请人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
发明人： Mark G. Johnson , Thomas H. Lee , Vivek Subramanian , Paul Michael Farmwald , James M. Cleeves
IPC分类号： G11C1700
CPC分类号： H01L27/1021 , G11C11/5692 , G11C17/14 , G11C17/16 , G11C2213/71 , H01L27/0203 , H01L27/115
摘要： An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.
摘要翻译：集成电路器件包括三维存储器阵列和阵列端子电路，用于向阵列的选定存储单元提供不同于读取电压的写入电压。两个电压都不一定等于提供给集成电路的VDD电源电压。特别是如果大于VDD的写入电压可以由片上电压发生器（例如电荷泵）产生，其可能需要不期望的大量管芯面积，特别是相对于较高位密度的三维存储器阵列完全以半导体衬底上的层形成。在几个优选实施例中，存储器阵列正下方的区域有利地用于布置写入电压发生器中的至少一些，从而在写入操作期间将发生器定位在选定的存储器单元附近。

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