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21. 发明授权

US07821343B1 Transmitter with multiple phase locked loops 有权
标题翻译：具有多个锁相环的变送器
公开(公告)号：US07821343B1
公开(公告)日：2010-10-26
申请号：US12229813
申请日：2008-08-27
申请人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
发明人： Wilson Wong , Sergey Shumarayev , Allen Chan , Weiqi Ding
IPC分类号： H03L7/00
CPC分类号： H03L7/23
摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.
摘要翻译：描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出或第二PLL的输出。在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。在宽范围模式下，需要较宽的频率范围。另一方面，在低抖动模式中，需要低抖动。

22. 发明申请

US20100079200A1 PROCESS/DESIGN METHODOLOGY TO ENABLE HIGH PERFORMANCE LOGIC AND ANALOG CIRCUITS USING A SINGLE PROCESS 有权
标题翻译：使用单一过程实现高性能逻辑和模拟电路的过程/设计方法
公开(公告)号：US20100079200A1
公开(公告)日：2010-04-01
申请号：US12241706
申请日：2008-09-30
申请人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
发明人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
IPC分类号： G05F1/10 , H01L21/336
CPC分类号： G05F3/205 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
摘要翻译：提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

23. 发明授权

US09680675B1 Methods and apparatus for automated adaptation of transmitter equalizer tap settings 有权
公开(公告)号：US09680675B1
公开(公告)日：2017-06-13
申请号：US13597618
申请日：2012-08-29
申请人： Donald Alderrou , Peng Li , Weiqi Ding
发明人： Donald Alderrou , Peng Li , Weiqi Ding
IPC分类号： H04L27/01
CPC分类号： H04B1/38 , H04B17/309 , H04L25/03343 , H04L25/03885 , H04L27/01
摘要： One embodiment relates to a method of automated adaptation of a transmitter equalizer. A multi-dimensional search space of tap settings for the transmitter equalizer is divided into multiple single-dimensional search spaces, each single-dimensional search space being associated with a single tap of the transmitter equalizer. The multiple single-dimensional search spaces are searched in series, and a tap for a single-dimensional search space is set before searching a next single-dimensional search space. Another embodiment relates to a transceiver with adaptation circuitry configured to implement the above-described method. Other embodiments, aspects, and features are also disclosed.

24. 发明授权

US08836443B2 Integrated circuits with configurable inductors 有权
标题翻译：具有可配置电感器的集成电路
公开(公告)号：US08836443B2
公开(公告)日：2014-09-16
申请号：US13617347
申请日：2012-09-14
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Ali Atesoglu , Sharat Babu Ippili
IPC分类号： H01L23/66 , H03B5/08 , H03C3/22 , H01F27/29 , H03B5/12 , H01F27/28 , H01F21/12
CPC分类号： H03B5/1212 , H01F2021/125 , H01F2027/2809 , H01L2924/0002 , H03B5/1243 , H03B5/1268 , H01L2924/00
摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.
摘要翻译：提供具有锁相环的集成电路。锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。多个电感器中选择的一个可以主动地连接到振荡器电路。压控振荡器可以具有多个振荡器电路。每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

25. 发明授权

US08674862B1 Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter 有权
标题翻译：逐次逼近寄存器模数转换器的数字校准系统和方法
公开(公告)号：US08674862B1
公开(公告)日：2014-03-18
申请号：US13604446
申请日：2012-09-05
申请人： Wei Li , Weiqi Ding , Yanjing Ke
发明人： Wei Li , Weiqi Ding , Yanjing Ke
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/00 , H03M1/10 , H03M1/1061 , H03M1/12 , H03M1/38 , H03M1/804
摘要： Systems and methods of calibrating a successive approximation register analog-to-digital converter (ADC) are disclosed. A plurality of capacitor stages, a first capacitor array, and a first capacitor stage are coupled in parallel. A capacitance of the first capacitor stage is compared to a sum of capacitances of the plurality of capacitor stages and of the first capacitor array. In response to the comparing, the capacitance of the first capacitor stage is increased by increasing the capacitance of a second capacitor array if the capacitance of the first capacitor stage is less than the sum of the capacitances of the plurality of capacitor stages and of the first capacitor array.
摘要翻译：公开了校准逐次逼近寄存器模数转换器（ADC）的系统和方法。多个电容器级，第一电容器阵列和第一电容器级并联耦合。将第一电容器级的电容与多个电容器级和第一电容器阵列的电容之和进行比较。响应于比较，如果第一电容器级的电容小于多个电容器级的电容和第一电容器级的电容之和，则通过增加第二电容器阵列的电容来增加第一电容器级的电容电容阵列。

26. 发明授权

US08184651B2 PLD architecture optimized for 10G Ethernet physical layer solution 有权
标题翻译：针对10G以太网物理层解决方案优化的PLD架构
公开(公告)号：US08184651B2
公开(公告)日：2012-05-22
申请号：US12100360
申请日：2008-04-09
申请人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
发明人： Allen Chan , Sergey Shumarayev , Wilson Wong , Weiqi Ding
IPC分类号： H04L12/56
CPC分类号： H04L49/30 , H04L49/352
摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the transceiver circuitry may be configured to implement the physical (PHY) layer of the 10 GbE networking specification. This integrated circuit may then be coupled to an optical transceiver module in order to transmit and receive 10 GbE optical signals. The transceiver circuitry and interface circuitry that connects the transceiver circuitry with the programmable circuitry may be hard-wired or partially hard-wired.
摘要翻译：集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和10千兆以太网（10GbE）收发器电路。可编程电路和收发器电路可以被配置为实现10GbE网络规范的物理（PHY）层。该集成电路然后可以耦合到光收发器模块，以便发送和接收10GbE光信号。将收发器电路与可编程电路连接的收发器电路和接口电路可以是硬接线或部分硬接线的。

27. 发明授权

US08174294B1 Configurable buffer circuits and methods 有权
标题翻译：可配置缓冲电路和方法
公开(公告)号：US08174294B1
公开(公告)日：2012-05-08
申请号：US12910177
申请日：2010-10-22
申请人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
发明人： Weiqi Ding , Yanjing Ke , Sergey Shumarayev
IPC分类号： H03B1/00
CPC分类号： H04L25/0272
摘要： A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circuit coupled to the first and the second resistors. The third switch circuit couples the first and the second resistors to a node at a first voltage when the buffer circuit is configured to function in a current mode logic buffer mode. The third switch circuit couples the first and the second resistors to a node at a second voltage when the buffer circuit is configured to function in an H-bridge buffer mode.
摘要翻译：缓冲电路包括电流源电路，耦合到电流源电路的第一和第二开关电路，耦合到第一开关电路的第一电阻器，耦合到第二开关电路的第二电阻器和耦合到第二开关电路的第三开关电路，第一和第二电阻。当缓冲电路被配置为以当前模式逻辑缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第一电压的节点。当缓冲电路被配置为以H桥缓冲器模式工作时，第三开关电路将第一和第二电阻器耦合到第二电压的节点。

28. 发明申请

US20110235756A1 SIGNAL LOSS DETECTOR FOR HIGH-SPEED SERIAL INTERFACE OF A PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：用于可编程逻辑器件高速串行接口的信号丢失检测器
公开(公告)号：US20110235756A1
公开(公告)日：2011-09-29
申请号：US13151717
申请日：2011-06-02
申请人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
发明人： Weiqi Ding , Sergey Shumarayev , Wilson Wong , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H04L27/06
CPC分类号： H04L25/45
摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.
摘要翻译：信号丢失检测器包括对输入数据进行数字和模拟监测。输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

29. 发明授权

US07952423B2 Process/design methodology to enable high performance logic and analog circuits using a single process 有权
标题翻译：使用单一过程实现高性能逻辑和模拟电路的过程/设计方法
公开(公告)号：US07952423B2
公开(公告)日：2011-05-31
申请号：US12241706
申请日：2008-09-30
申请人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
发明人： Qi Xiang , Albert Ratnakumar , Jeffrey Xiaoqi Tung , Weiqi Ding
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.
摘要翻译：提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

30. 发明授权

US07759972B1 Integrated circuit architectures with heterogeneous high-speed serial interface circuitry 有权
标题翻译：具有异构高速串行接口电路的集成电路架构
公开(公告)号：US07759972B1
公开(公告)日：2010-07-20
申请号：US11981934
申请日：2007-10-31
申请人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
发明人： Sergey Shumarayev , Wilson Wong , Weiqi Ding , Thungoc M. Tran , Tim Tri Hoang
IPC分类号： H01L25/00
CPC分类号： H03K19/177
摘要： An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。这些传统块离开设备的至少一个角落，不被这种遗留电路占用。这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

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