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21. 发明申请

US20140264913A1 Semiconductor Device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20140264913A1
公开(公告)日：2014-09-18
申请号：US13833464
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.
摘要翻译：半导体器件包括衬底，穿透衬底的穿硅通孔（TSV），从顶部穿过TSV的至少一个第一互连结构，并将TSV正上方的区域划分成若干子区域并被配置用于互连路由有源器件和多个第二互连结构占据TSV正上方的子区域并且被配置为将TSV电耦合到较高级互连。

22. 发明授权

US08283110B2 Method for fabricating an image sensor device 有权
标题翻译：图像传感器装置的制造方法
公开(公告)号：US08283110B2
公开(公告)日：2012-10-09
申请号：US12816743
申请日：2010-06-16
申请人： Ming-Sheng Yang , Ya-Yun Yu
发明人： Ming-Sheng Yang , Ya-Yun Yu
IPC分类号： G03F7/20
CPC分类号： H01L27/14685 , H01L27/14627 , H01L27/14698
摘要： A method for fabricating an image sensor device is disclosed. The method for fabricating an image sensor device comprises forming a photosensitive layer on a substrate. The photosensitive layer is exposed through a first photomask to form an exposed portion and an unexposed portion. The unexposed portion is partially exposed through a second photomask to form a trimmed part, wherein the second photomask comprise a first segment and a second segment that has a transmittance greater than that of the first segment. The trimmed part is removed to form photosensitive structures. The photosensitive structures are reflowed to form a first microlens and a second microlens having different heights.
摘要翻译：公开了一种用于制造图像传感器装置的方法。图像传感器装置的制造方法包括在基板上形成感光层。感光层通过第一光掩模曝光以形成曝光部分和未曝光部分。未曝光部分通过第二光掩模部分曝光以形成修剪部分，其中第二光掩模包括第一光栅和第二光栅，其具有大于第一光栅的透射率。去除修剪的部分以形成光敏结构。光敏结构被回流以形成具有不同高度的第一微透镜和第二微透镜。

23. 发明授权

US06616510B2 Chemical mechanical polishing method for copper 有权
公开(公告)号：US06616510B2
公开(公告)日：2003-09-09
申请号：US09735323
申请日：2000-12-12
申请人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
发明人： Chia-Lin Hsu , Teng-Chun Tsai , Yung-Tsung Wei , Ming-Sheng Yang
IPC分类号： H01L21465
CPC分类号： H01L21/3212 , B24B37/044 , C09G1/02
摘要： A chemical-mechanical polishing method for polishing a copper oxide layer and a copper layer. The copper oxide layer above the copper layer is first polished using an aqueous solution having a high concentration of polishing particles/chelating agent. The copper layer is then polished using a polishing slurry having a low concentration of polishing particles/chelating agent or the polishing slurry free of polishing particles/chelating agent. Alternatively, the copper oxide layer is polished using a mixture of the aqueous solution and the polishing slurry. After the copper oxide layer is removed, the copper layer is polished using the polishing slurry alone.

24. 发明授权

US06440861B1 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06440861B1
公开(公告)日：2002-08-27
申请号：US09652471
申请日：2000-08-31
申请人： Chih-Chien Liu , Jui-Tsen Huang , Yi-Fang Cheng , Ming-Sheng Yang
发明人： Chih-Chien Liu , Jui-Tsen Huang , Yi-Fang Cheng , Ming-Sheng Yang
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1063
摘要： A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer.
摘要翻译：形成双镶嵌结构的方法。第一电介质层和第二电介质层依次形成在衬底上。在第二介电层上形成第一光致抗蚀剂层。进行光刻和蚀刻操作以去除第二介电层和第一介电层的一部分，从而形成通孔。保形第三电介质层涂覆在第二电介质层的表面和通孔开口的内表面上。保形第三电介质层形成衬里电介质层。在第二电介质层上形成第二光致抗蚀剂层，然后对第二光致抗蚀剂层进行图案化。使用图案化的第二光致抗蚀剂层作为掩模，去除第二介电层的一部分以形成沟槽。去除图案化的第二光致抗蚀剂层。导电材料沉积在衬底上以填充通孔和沟槽。最后，进行化学机械抛光以除去第二介电层上方的多余的导电材料。

25. 发明授权

US06380069B1 Method of removing micro-scratch on metal layer 有权
标题翻译：去除金属层上的微划痕的方法
公开(公告)号：US06380069B1
公开(公告)日：2002-04-30
申请号：US09483581
申请日：2000-01-14
申请人： Hsueh-Chung Chen , Yung-Tsung Wei , Ming-Sheng Yang
发明人： Hsueh-Chung Chen , Yung-Tsung Wei , Ming-Sheng Yang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： A method of removing the micro-scratches on a metal layer is described, wherein the metal layer is formed on a barrier layer conformally onto a dielectric layer having a hole thereon, and wherein the metal layer over-fills the hole. The method comprises three chemical-mechanical polishing steps as described hereinbelow. The first chemical-mechanical polishing step is that oxidizing and polishing away the metal layer outside the hole, with a first slurry, wherein the first slurry has a chemical solution and has a plurality of abrasive particles. The second chemical-mechanical polishing step is that polishing away the barrier layer outside the hole, with a second slurry, whereby a plurality of micro-scratches are formed on the metal layer after the barrier layer is chemical-mechanically polished. The third chemical-mechanical polishing step is that buffing the metal layer, with the first slurry, thereby removing the micro-scratches on the metal layer.
摘要翻译：描述了去除金属层上的微划痕的方法，其中金属层在阻挡层上保形地形成在其上具有孔的电介质层上，并且其中金属层过满填充孔。该方法包括如下所述的三个化学 - 机械抛光步骤。第一化学机械抛光步骤是利用第一浆料氧化和抛光孔外的金属层，其中第一浆料具有化学溶液并具有多个研磨颗粒。第二化学机械抛光步骤是利用第二浆料抛光孔外的阻挡层，由此在阻挡层被化学机械抛光之后在金属层上形成多个微划痕。第三化学机械抛光步骤是用第一浆料抛光金属层，从而去除金属层上的微划痕。

26. 发明授权

US06200653B1 Method of forming an intermetal dielectric layer 失效
公开(公告)号：US06200653B1
公开(公告)日：2001-03-13
申请号：US09471055
申请日：1999-12-22
申请人： Cheng-Yuan Tsai , Chih-Chien Liu , Ming-Sheng Yang
发明人： Cheng-Yuan Tsai , Chih-Chien Liu , Ming-Sheng Yang
IPC分类号： H05H124
CPC分类号： H01L21/02131 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31053 , H01L21/31629 , H01L21/76801 , H01L21/76829
摘要： A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

27. 发明授权

US06197681B1 Forming copper interconnects in dielectric materials with low constant dielectrics 有权
标题翻译：在具有低常数电介质的介电材料中形成铜互连
公开(公告)号：US06197681B1
公开(公告)日：2001-03-06
申请号：US09477111
申请日：1999-12-31
申请人： Chih-Chien Liu , Cheng-Yuan Tsai , Ming-Sheng Yang
发明人： Chih-Chien Liu , Cheng-Yuan Tsai , Ming-Sheng Yang
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76811
摘要： A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a second dielectric layer is formed and an anti-reflective layer is formed. Then, a hardmask layer is formed. Etching of the hardmask layer is carried out. The photoresist layer is removed and another photoresist is replaced. The anti-reflective layer, the second dielectric layer and the first dielectric layer are all etched. The hardmask layer, the anti-reflective layer and the second dielectric layer are all etched. The photoresist layer, the hardmask layer and the anti-reflective layer are all removed. A first barrier layer is conformably formed on the sidewalls and the exposed surfaces of the second dielectric layer and the first dielectric layer, and on the surface of the first copper layer. A seed layer is conformably formed on the barrier layer. The via opening is filled up and the line opening with a second copper layer. Finally, the second copper layer can be planarized until the second dielectric layer is exposed.
摘要翻译：公开了一种用于形成铜互连的方法。该方法包括：首先提供半导体衬底。然后，形成第一电介质层。接着，形成第二电介质层，形成抗反射层。然后，形成硬掩模层。执行硬掩模层的蚀刻。去除光致抗蚀剂层并替换另一种光致抗蚀剂。抗反射层，第二介电层和第一介电层全部被蚀刻。硬掩模层，抗反射层和第二介电层全部被蚀刻。光致抗蚀剂层，硬掩模层和抗反射层全部被去除。第一阻挡层顺应地形成在第二介电层和第一介电层的侧壁和暴露表面上以及在第一铜层的表面上。种子层顺应地形成在阻挡层上。通孔开口被填满，线路开口带有第二铜层。最后，第二铜层可以被平坦化，直到暴露第二介电层。

28. 发明授权

US09030025B2 Integrated circuit layout 有权
标题翻译：集成电路布局
公开(公告)号：US09030025B2
公开(公告)日：2015-05-12
申请号：US13834495
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L23/5286 , H01L2224/13 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout comprises a through silicon via (TSV) configured to couple positive operational voltage VDD (VDD TSV), a through silicon via (TSV) configured to couple operational signals (signal TSV), a plurality of through silicon vias (TSVs) configured to couple operational voltage VSS (VSS TSVs) around the VDD TSV and the signal TSV and one or more backside redistribution lines (RDLs) connecting the VSS TSVs together to form a web-like heat dissipating structure at least surrounding the VDD TSV and the signal TSV.
摘要翻译：集成电路布局包括被配置为耦合正工作电压VDD（VDD TSV）的通硅通孔（TSV），被配置为耦合操作信号（信号TSV）的多通硅通孔（TSV）被配置为将VDD TSV和信号TSV以及将VSS TSV连接在一起的一个或多个背面再分配线（RDL）耦合到工作电压VSS（VSS TSV），以形成至少围绕VDD TSV的网状散热结构，并且信号TSV。

29. 发明授权

US08890607B2 Stacked chip system 有权
标题翻译：堆叠芯片系统
公开(公告)号：US08890607B2
公开(公告)日：2014-11-18
申请号：US13835055
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/538 , H01L23/52 , H01L23/50
CPC分类号： H01L23/50 , H01L23/481 , H01L2225/06544 , H01L2924/0002 , H01L2924/00
摘要： A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
摘要翻译：提供堆叠式芯片系统以包括第一芯片，第二芯片，连接第一芯片和第二芯片的第一组直通硅通孔（TSV），并且包括至少一个第一VSS TSV，至少一个第一VDD TSV，多个第一信号TSV和连接第一芯片和第二芯片的至少一个第一冗余TSV和第二组穿通硅通孔（TSV），并且包括至少一个第二VSS TSV，至少一个第二VDD TSV，多个第二信号TSV和至少一个第二冗余TSV，其中所有所述第一组TSV由被配置为选择所述至少一个第一冗余TSV并绕过所述第一组TSV的其余部分中的至少一个的第一选择电路耦合，以及其中所述至少一个第一冗余TSV和所述至少第二冗余TSV由被配置为允许它们中的一个替换另一个的第二选择电路耦合。

30. 发明申请

US20140264630A1 Integrated Structure 审中-公开
标题翻译：综合结构
公开(公告)号：US20140264630A1
公开(公告)日：2014-09-18
申请号：US13832844
申请日：2013-03-15
申请人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
发明人： Chao-Yuan Huang , Yueh-Feng Ho , Ming-Sheng Yang , Hwi-Huang Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate.
摘要翻译：集成结构包括依次包括第一电介质层和第二电介质盖层的衬底，在衬底上具有高k栅极电介质层的金属栅极晶体管，嵌入在第一介电层内的栅电极和源极 /漏极，穿过第一介电层并与源极/漏极直接接触的第一金属触点和穿过第二电介质盖层，第一电介质层和衬底的贯穿硅。

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