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21. 发明授权

US07214983B2 Non-volatile memory and fabricating method thereof 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US07214983B2
公开(公告)日：2007-05-08
申请号：US10904703
申请日：2004-11-24
申请人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
发明人： Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu , Meng-Hsuan Weng
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/0207 , H01L27/11521 , H01L27/11568
摘要： A method of fabricating a non-volatile memory is provided. A plurality of stack gate strips is formed on a substrate and a plurality of source/drain regions is formed in the substrate beside the stack gate strips. A plurality of dielectric strips is formed on the source/drain regions. A plurality of word lines is formed on the stack gate strips and the dielectric strips. Thereafter, the stack gate strips exposed by the word lines are removed to form a plurality of openings. A plurality of spacers is formed on the sidewalls of the openings and the word lines. A dielectric layer is formed over the substrate. A plurality of contacts is formed in the dielectric layer and the dielectric strips between two adjacent word lines.
摘要翻译：提供了一种制造非易失性存储器的方法。在基板上形成多个堆叠栅极条，并且在堆叠栅极条旁边的基板上形成多个源极/漏极区域。在源/漏区上形成多个介质条。多个字线形成在堆叠栅极条和介质条上。此后，除去由字线露出的堆叠栅极条以形成多个开口。在开口和字线的侧壁上形成多个间隔物。介电层形成在衬底上。在电介质层和两个相邻字线之间的介质条形成多个触点。

22. 发明授权

US08466508B2 Non-volatile memory structure including stress material between stacked patterns 有权
标题翻译：非易失性存储器结构，包括层叠图案之间的应力材料
公开(公告)号：US08466508B2
公开(公告)日：2013-06-18
申请号：US11866756
申请日：2007-10-03
申请人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
发明人： Shaw-Hung Ku , Shih-Chin Lee , Chia-Wei Wu , Shang-Wei Lin , Tzung-Ting Han , Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/792 , H01L29/788 , H01L21/762
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.
摘要翻译：提供了包括基板，堆叠图案和应力图案的非易失性存储器结构。层叠图案设置在基板上。每个堆叠图案包括电荷存储结构和从底部到顶部的栅极。这里，电荷存储结构至少包括电荷存储层。应力图案分别设置在两个相邻堆叠图案之间的基板上。

23. 发明授权

US07592036B2 Method for manufacturing NAND flash memory 有权
标题翻译：制造NAND闪存的方法
公开(公告)号：US07592036B2
公开(公告)日：2009-09-22
申请号：US11435459
申请日：2006-05-16
申请人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
发明人： Kuei-Yun Chen , Chun-Lien Su , Yin-Jen Chen , Ming-Shang Chen
IPC分类号： B05D5/12
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.
摘要翻译：提供一种制造NAND闪速存储器的方法。首先，提供基板。接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。接下来，在隔离结构的暴露的侧壁上形成第二导电层。接下来，在衬底上依次形成栅极间电介质层和第三导电层。

24. 发明申请

US20090011594A1 Methods of Trench and Contact Formation in Memory Cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US20090011594A1
公开(公告)日：2009-01-08
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/768
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

25. 发明授权

US07399674B2 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US07399674B2
公开(公告)日：2008-07-15
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

26. 发明申请

US20060086968A1 Method of fabricating NAND-type flash EEPROM without field oxide isolation 有权
标题翻译：制造没有场氧化物隔离的NAND型快闪EEPROM的方法
公开(公告)号：US20060086968A1
公开(公告)日：2006-04-27
申请号：US10971465
申请日：2004-10-22
申请人： Ming-Shang Chen , Wen-Pin Lu
发明人： Ming-Shang Chen , Wen-Pin Lu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.
摘要翻译：描述了用于制造没有场氧化物隔离的NAND型EEPROM的方法。采用P +注入来隔离相邻的记忆细胞。

27. 发明授权

US06677211B2 Method for eliminating polysilicon residue 有权
标题翻译：消除多晶硅残渣的方法
公开(公告)号：US06677211B2
公开(公告)日：2004-01-13
申请号：US10043144
申请日：2002-01-14
申请人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
发明人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28123 , H01L21/3211 , H01L21/32155 , H01L21/76888 , H01L21/76895 , H01L27/115
摘要： A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon nitride in two steps. A tilted ion implantation step is performed to implant nitrogen ions into the polysilicon residue to rich nitrogen containing of the polysilicon residue. A nitrogen anneal step is subsequently performed to completely convert the rich nitrogen containing polysilicon residue into silicon nitride that can eliminate the conductivity of the polysilicon residue and prevent conventional oxygen encroachment occurring.
摘要翻译：通过两步来将多晶硅残渣转化为氮化硅来提供消除多晶硅残渣的方法。进行倾斜离子注入步骤以将氮离子注入到多晶硅残渣中以富含多晶硅残渣的氮。随后进行氮退火步骤以将富含氮的多晶硅残留物完全转化成氮化硅，其可以消除多晶硅残余物的导电性并防止发生常规的氧侵蚀。

28. 发明授权

US06642118B2 Method for eliminating polysilicon residue by fully converting the polysilicon into silicon dioxide 有权
标题翻译：通过将多晶硅完全转化为二氧化硅来消除多晶硅残渣的方法
公开(公告)号：US06642118B2
公开(公告)日：2003-11-04
申请号：US10043145
申请日：2002-01-14
申请人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
发明人： Chun-Lien Su , Chun-Chi Wang , Ming-Shang Chen
IPC分类号： H01L21336
CPC分类号： H01L27/115 , H01L21/26506 , H01L21/26586 , H01L21/32105 , H01L21/76895 , H01L27/112 , H01L27/11521
摘要： A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.
摘要翻译：通过两步将多晶硅残渣转化为二氧化硅，提供消除多晶硅残渣的方法。进行倾斜离子注入步骤以将氧离子注入到多晶硅残渣中，以富含含有多晶硅残渣的富氧。随后进行氧还原步骤以将富含氧的多晶硅残余物完全转化为二氧化硅，其可以消除多晶硅残余物的导电性并防止发生氧侵蚀。

29. 发明授权

US08593850B2 Diode-less array for one-time programmable memory 有权
公开(公告)号：US08593850B2
公开(公告)日：2013-11-26
申请号：US12346706
申请日：2008-12-30
申请人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
发明人： Kuan-Fu Chen , Yin-Jen Chen , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： G11C17/00 , G11C17/06 , G11C17/18
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

30. 发明授权

US07666784B2 Methods of trench and contact formation in memory cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US07666784B2
公开(公告)日：2010-02-23
申请号：US12211603
申请日：2008-09-16
申请人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
发明人： Miao-Chih Hsu , Tzung-Ting Han , Ming-Shang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area.
摘要翻译：使用这种方法形成的接触形成方法和记忆阵列，该方法包括提供具有接触区域的基底; 形成沿第一方向延伸的多个线状结构; 在线形结构旁边形成硬掩模间隔物; 在硬掩模间隔物上形成绝缘材料层; 在绝缘材料层中形成连续的沟槽，该沟槽沿与第一方向不同的第二方向延伸并暴露接触区域; 以及在所述沟槽中形成导电线以接触所述接触区域。

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