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21. 发明授权

US08378756B2 Drive loop for MEMS oscillator 有权
标题翻译： MEMS振荡器的驱动环路
公开(公告)号：US08378756B2
公开(公告)日：2013-02-19
申请号：US12782064
申请日：2010-05-18
申请人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chiang Pu , Chan-Hong Chern , Chih-Chang Lin , Yuwen Swei
IPC分类号： H03B5/30 , G01C19/00
CPC分类号： H03B5/30
摘要： Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.
摘要翻译：一些实施例涉及一种方法，包括：根据MEMS装置的移动产生电流; 移动由控制信号控制; 根据电流产生峰值电压; 以及当峰值电压超出预定范围时调节控制信号。

22. 发明授权

US08354862B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08354862B2
公开(公告)日：2013-01-15
申请号：US13448878
申请日：2012-04-17
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.
摘要翻译：包括被配置为接收输入信号和时钟的第一，第三和第五相位时钟并且产生指示时钟的第一早期信号的第一电路的电路早于输入信号，并且指示时钟的第一晚信号晚于输入信号。电路还包括配置成接收时钟的输入信号和第二，第四和第六相位时钟的第二电路，并且产生指示时钟早于输入信号的第二早期信号，并且指示时钟的第二延迟信号是晚于输入信号。电路还包括被配置为产生第一增加信号的第三电路。电路还包括被配置为产生第一减小信号的第四电路。

23. 发明授权

US08179162B2 Phase-lock assistant circuitry 有权
标题翻译：锁相辅助电路
公开(公告)号：US08179162B2
公开(公告)日：2012-05-15
申请号：US12835130
申请日：2010-07-13
申请人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
发明人： Chih-Chang Lin , Chan-Hong Chern , Steven Swei , Ming-Chieh Huang , Tien-Chun Yang
IPC分类号： H03D13/00 , H03L7/06
CPC分类号： H03L7/08 , H03L7/081 , H03L7/087
摘要： Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.
摘要翻译：一些实施例涉及一种电路，包括：第一电路，其被配置为将输出时钟的频率锁定到参考时钟的频率; 第二电路，被配置为将输入信号与所述输出时钟的相位时钟对准; 第三电路，被配置为使用所述输出时钟的第一组相位时钟和所述输出时钟的第二组相位时钟，以改善所述输入信号与所述输出时钟的相位时钟的对准; 以及锁定检测电路，被配置为当所述输出时钟的频率未被锁定到所述参考时钟的频率时接通所述第一电路; 并且当输出时钟的频率被锁定到参考时钟的频率时，关闭第一电路并接通第二电路和第三电路。

24. 发明授权

US08115545B2 Automatic level control 有权
标题翻译：自动电平控制
公开(公告)号：US08115545B2
公开(公告)日：2012-02-14
申请号：US13177958
申请日：2011-07-07
申请人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
发明人： Chiang Pu , Ming-Chieh Huang , Chan-Hong Chern , Tien-Chun Yang
IPC分类号： H03F1/36
CPC分类号： G01C19/5776
摘要： Some embodiments regard a circuit comprising: a high voltage transistor providing a resistance; an amplifier configured to receive a current and to convert the current to a first voltage that is used in a loop creating the current; and an automatic level control circuit that, based on an AC amplitude of the first voltage, adjusts a second voltage at a gate of the high voltage transistor and thereby adjusts the resistance and the first voltage; wherein the automatic level control circuit is configured to adjust the first voltage toward the first reference voltage if the first voltage differs from a first reference voltage.
摘要翻译：一些实施例涉及一种电路，包括：提供电阻的高压晶体管; 放大器，被配置为接收电流并将电流转换成在产生电流的环路中使用的第一电压; 以及自动电平控制电路，其基于所述第一电压的交流振幅调整所述高电压晶体管的栅极处的第二电压，从而调整所述电阻和所述第一电压; 其中所述自动电平控制电路被配置为如果所述第一电压与第一参考电压不同，则将所述第一电压调整为朝向所述第一参考电压。

25. 发明申请

US20110199152A1 INTEGRATED CIRCUITS INCLUDING A CHARGE PUMP CIRCUIT AND OPERATING METHODS THEREOF 有权
标题翻译：集成电路，包括充电泵电路及其工作方法
公开(公告)号：US20110199152A1
公开(公告)日：2011-08-18
申请号：US12706886
申请日：2010-02-17
申请人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
发明人： Steven SWEI , Chih-Chang Lin , Tien-Chun Yang , Chan-Hong Chern , Ming-Chieh Huang
IPC分类号： G05F1/10
CPC分类号： G05F1/10 , G05F3/02 , H03L7/0895 , H03L7/0896 , H03L7/0898
摘要： An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
摘要翻译：集成电路包括第一电流源。第二电流源经由导线与第一电流源电耦合。开关电路耦合在第一电流源和第二电流源之间。第一电路耦合在第一节点和第二节点之间。第一节点设置在第一电流源和开关电路之间。第二节点与第一电流源耦合。第一电路被配置为基本上均衡第一节点和第二节点上的电压。第二电路耦合在第三节点和第四节点之间。第三节点设置在第二电流源和开关电路之间。第四节点被布置成与第二电流源耦合。第二电路被配置为基本上均衡第三节点和第四节点上的电压。

26. 发明申请

US20100214857A1 MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF 有权
标题翻译：记忆电路，系统及其接入方法
公开(公告)号：US20100214857A1
公开(公告)日：2010-08-26
申请号：US12698423
申请日：2010-02-02
申请人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
发明人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1042 , G11C8/04
摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
摘要翻译：交错存储器电路包括具有第一存储单元的第一存储器组。第一本地控制电路与第一存储体耦合。第二存储器组包括第二存储器单元。第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。全局控制电路与第一和第二本地控制电路耦合。交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一读取列选择信号RSSL用于访问第一个存储单元。

27. 发明授权

US09489989B2 Voltage regulators, memory circuits, and operating methods thereof 有权
标题翻译：电压调节器，存储器电路及其操作方法
公开(公告)号：US09489989B2
公开(公告)日：2016-11-08
申请号：US12820712
申请日：2010-06-22
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tien Chun Yang , Chih-Chang Lin , Yuwen Swei
IPC分类号： G11C11/22 , G11C11/24 , G11C7/06 , G11C5/14 , G11C8/00
CPC分类号： G11C11/4074 , G11C5/147
摘要： A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
摘要翻译：电压调节器包括与电压调节器的输出端电耦合的输出级。输出级包括具有体积和漏极的至少一个晶体管。至少一个背偏置电路与所述至少一个晶体管的主体电耦合。至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

28. 发明授权

US08854104B2 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US08854104B2
公开(公告)日：2014-10-07
申请号：US13793681
申请日：2013-03-11
申请人： Tao Wen Chung , Chan-Hong Chern , Tsung-Ching (Jim) Huang , Chih-Chang Lin , Ming-Chieh Huang
发明人： Tao Wen Chung , Chan-Hong Chern , Tsung-Ching (Jim) Huang , Chih-Chang Lin , Ming-Chieh Huang
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K3/356182 , H03K17/102 , H03K19/018521
摘要： A circuit includes a first capacitive device and a first latch. The first capacitive device includes a first end configured to receive a first input signal and a second end coupled with the first latch. The first latch includes a first transistor and a second transistor that are of a first type. A first terminal of the first transistor and a first terminal of the second transistor are each configured to receive a first voltage value. A second terminal of the first transistor is coupled with a third terminal of the second transistor. A third terminal of the first transistor is coupled with a second terminal of the second transistor and with the second end of the capacitive device, and is configured to provide an output voltage for the first latch.
摘要翻译：电路包括第一电容性装置和第一锁存器。第一电容性装置包括被配置为接收第一输入信号的第一端和与第一锁存器耦合的第二端。第一锁存器包括第一类型的第一晶体管和第二晶体管。第一晶体管的第一端子和第二晶体管的第一端子都被配置为接收第一电压值。第一晶体管的第二端与第二晶体管的第三端耦合。第一晶体管的第三端子与第二晶体管的第二端子和电容器件的第二端耦合，并且被配置为提供用于第一锁存器的输出电压。

29. 发明授权

US08766613B2 Method of operating voltage regulator 有权
标题翻译：操作电压调节器的方法
公开(公告)号：US08766613B2
公开(公告)日：2014-07-01
申请号：US13744037
申请日：2013-01-17
申请人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
发明人： Chan-Hong Chern , Tzu-Ching Chang , Min-Shueh Yuan , Yuwen Swei , Chih-Chang Lin , Chiang Pu , Ming-Chieh Huang , Kuoyuan Hsu
IPC分类号： G05F1/44
CPC分类号： H02M3/158 , G05F1/44 , G05F1/56
摘要： A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.
摘要翻译：一种操作电压调节器电路的方法包括由稳压器电路的放大器产生控制信号。控制信号基于放大器的反相输入处的参考信号和放大器的非反相输入端的反馈信号而产生。通过响应于控制信号的驱动器产生朝向电压调节器电路的输出节点流动的驱动电流，并且驱动器耦合在第一功率节点和输出节点之间。响应于输出节点处的电压电平产生反馈信号。耦合在输出节点和第二功率节点之间的晶体管在电压调节器电路工作期间的一段时间内使其工作在饱和模式。

30. 发明授权

US08625240B2 Input/output circuit with inductor 有权
标题翻译：带电感的输入/输出电路
公开(公告)号：US08625240B2
公开(公告)日：2014-01-07
申请号：US13293853
申请日：2011-11-10
申请人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
发明人： Tao Wen Chung , Chan-Hong Chern , Ming-Chieh Huang , Chih-Chang Lin , Yuwen Swei
IPC分类号： H02H3/22
CPC分类号： H02H9/04 , H01L23/60 , H01L27/0248 , H01L2924/0002 , H03F2200/294 , H03F2203/45638 , H03G1/0023 , H03K3/35613 , H03K19/018514 , H01L2924/00
摘要： An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.
摘要翻译：输入/输出（I / O）电路包括与I / O电路的输出节点电耦合的静电放电（ESD）保护电路。至少一个电感器和至少一个负载以串联方式电耦合，并且在I / O电路的输出节点和电力线之间。电路与所述至少一个电感器和所述至少一个负载之间的节点电耦合。电路可操作以在信号转换期间增加流过至少一个电感器的电流。

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