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21. 发明授权

US07683491B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07683491B2
公开(公告)日：2010-03-23
申请号：US11943142
申请日：2007-11-20
申请人： Mikihiko Itoh , Masaru Koyanagi
发明人： Mikihiko Itoh , Masaru Koyanagi
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48599 , H01L2224/4911 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.
摘要翻译：该半导体器件的一个方面包括：封装基板，其具有在其上表面上施加有电源电压的多个焊盘;布置在封装基板上的第一存储芯片，以及设置在第一电源焊盘上的第一电源焊盘设置在垂直于第一侧的第二侧上的第一侧和第二电源焊盘，以及沿着第一存储芯片的第一和第二电源焊盘暴露的方向平移的第二存储芯片，其布置在第一存储器芯片，并且具有与第一存储器芯片相同的结构，其中第一和第二电源焊盘分别设置在第一存储器芯片的对角角。

22. 发明申请

US20080122064A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080122064A1
公开(公告)日：2008-05-29
申请号：US11943142
申请日：2007-11-20
申请人： Mikihiko Itoh , Masaru Koyanagi
发明人： Mikihiko Itoh , Masaru Koyanagi
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/0401 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/48599 , H01L2224/4911 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/14 , H01L2924/30105 , H01L2924/00
摘要： An aspect of the semiconductor device comprising a package substrate which has a plurality of pads to which a power supply voltage is applied on an upper surface thereof, a first memory chip which is arranged on the package substrate and has a first power supply pad provided on a first side and a second power supply pad provided on a second side perpendicular to the first side, and a second memory chip which is translated in a direction along which the first and second power supply pads of the first memory chip are exposed, arranged on the first memory chip, and has the same structure as the first memory chip, wherein the first and second power supply pads are provided at diagonal corners of the first memory chip, respectively.
摘要翻译：该半导体器件的一个方面包括：封装基板，其具有在其上表面上施加有电源电压的多个焊盘;布置在封装基板上的第一存储芯片，以及设置在第一电源焊盘上的第一电源焊盘设置在垂直于第一侧的第二侧上的第一侧和第二电源焊盘，以及沿着第一存储芯片的第一和第二电源焊盘暴露的方向平移的第二存储芯片，其布置在第一存储器芯片，并且具有与第一存储器芯片相同的结构，其中第一和第二电源焊盘分别设置在第一存储器芯片的对角角。

23. 发明授权

US07206242B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07206242B2
公开(公告)日：2007-04-17
申请号：US11013688
申请日：2004-12-17
申请人： Katsuki Matsudera , Kazuhide Yoneya , Masaru Koyanagi
发明人： Katsuki Matsudera , Kazuhide Yoneya , Masaru Koyanagi
IPC分类号： G11C7/00
CPC分类号： G11C7/1066 , G11C7/1006 , G11C7/1051 , G11C2207/107
摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.
摘要翻译：半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。输出寄存器与读取时钟同步地保存转换的读取数据。选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

24. 发明授权

US06700411B2 MOS-type semiconductor integrated circuit 失效
公开(公告)号：US06700411B2
公开(公告)日：2004-03-02
申请号：US10234106
申请日：2002-09-05
申请人： Katsuki Matsudera , Masaru Koyanagi
发明人： Katsuki Matsudera , Masaru Koyanagi
IPC分类号： H03K19094
CPC分类号： H03K19/0963 , H03K19/00315
摘要： An MOS-type semiconductor integrated circuit has two MOS transistors of the opposite conductivity channel types connected in series between a high-voltage potential terminal and a ground potential terminal. Those two MOS transistors constitute an inverter and their gates are connected together to an input node. As output nodes, first and second nodes are provided with a current path in between which includes transistors whose gates are connected to the high-voltage potential terminal. A current path including the first transistor which constitutes a switch is inserted between the first node and the output node, and a current path including the second transistor and a barrier transistor is inserted between the second node and the output node. The gates of the first and second transistors are respectively connected with complementary clock signals. The bate of the barrier transistor is connected to the high-voltage potential terminal.

25. 发明授权

US06563351B2 Semiconductor integrated circuit having output buffer 失效
公开(公告)号：US06563351B2
公开(公告)日：2003-05-13
申请号：US09965951
申请日：2001-09-27
申请人： Tadashi Onizawa , Natsuki Kushiyama , Masaru Koyanagi , Katsuki Matsudera
发明人： Tadashi Onizawa , Natsuki Kushiyama , Masaru Koyanagi , Katsuki Matsudera
IPC分类号： H03B100
CPC分类号： H03K19/01707 , H03K17/102 , H03K17/162
摘要： A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

26. 发明授权

US06510087B2 Semiconductor memory device 失效
公开(公告)号：US06510087B2
公开(公告)日：2003-01-21
申请号：US09963805
申请日：2001-09-25
申请人： Manami Kudou , Kazuhide Yoneya , Masaru Koyanagi , Toshiki Hisada , Katsuki Matsudera
发明人： Manami Kudou , Kazuhide Yoneya , Masaru Koyanagi , Toshiki Hisada , Katsuki Matsudera
IPC分类号： G11C700
CPC分类号： G11C7/106 , G11C7/1036 , G11C7/1051 , G11C7/1069 , G11C7/1072 , G11C7/222 , G11C2207/108 , G11C2207/2281
摘要： A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

27. 发明授权

US06272063B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06272063B1
公开(公告)日：2001-08-07
申请号：US09535952
申请日：2000-03-27
申请人： Kenichi Matoba , Masaru Koyanagi
发明人： Kenichi Matoba , Masaru Koyanagi
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A semiconductor memory device comprises a first core section including a plurality of memory cell arrays, a second core section including a plurality of memory cell arrays and provided below the first core section, a third core section including a plurality of memory cell arrays and provided in a right side of the first core section, and a fourth core section including a plurality of memory cell arrays and provided in a right side of the second core section, wherein at least a part of the memory cell arrays of the first core section and at least a part of the memory cell arrays of the fourth core section are simultaneously activated, and at least a part of the memory cell arrays of the second core section and at least a part of the memory cell arrays of the third core section are simultaneously activated.
摘要翻译：半导体存储器件包括：第一芯部分，包括多个存储单元阵列;第二芯部分，包括多个存储单元阵列并且设置在第一芯部下;第三核心部分，包括多个存储单元阵列，第一芯部的右侧，以及包括多个存储单元阵列并设置在第二芯部的右侧的第四芯部，其中，第一芯部的存储单元阵列的至少一部分和同时激活第四核心部分的存储单元阵列的至少一部分，并且第二核心部分的至少一部分存储单元阵列和第三核心部分的至少一部分存储单元阵列同时被激活。

28. 发明授权

US5357193A Semiconductor memory having a voltage stress applying circuit 失效
标题翻译：具有电压应力施加电路的半导体存储器
公开(公告)号：US5357193A
公开(公告)日：1994-10-18
申请号：US813523
申请日：1991-12-26
申请人： Hiroaki Tanaka , Masaru Koyanagi
发明人： Hiroaki Tanaka , Masaru Koyanagi
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30 , G01R31/3161 , G01R31/317 , G01R31/3185 , G11C11/401 , G11C11/4094 , G11C29/06 , G11C29/50 , H01L21/66 , G11C7/00
CPC分类号： G01R31/3161 , G01R31/2884 , G01R31/30 , G01R31/31712 , G01R31/31715 , G11C11/4094 , G11C29/50 , G11C11/401
摘要： An semiconductor device includes an integrated circuit having first and second circuit sections formed on a semiconductor chip, at least one voltage stress testing pad formed on the semiconductor chip for supplying a voltage stress testing voltage or signal to the first circuit section, and a control circuit formed on the semiconductor chip for controlling and setting the second circuit section into a state corresponding to a voltage stress testing mode by using an input from the voltage stress testing pads.
摘要翻译：半导体器件包括具有形成在半导体芯片上的第一和第二电路部分的集成电路，形成在半导体芯片上的用于向第一电路部分提供电压应力测试电压或信号的至少一个电压应力测试焊盘，以及控制电路形成在半导体芯片上，用于通过使用来自电压应力测试垫的输入来将第二电路部分控制和设置成对应于电压应力测试模式的状态。

29. 发明授权

US5202588A Substrate bias circuit 失效
标题翻译：基板偏置电路
公开(公告)号：US5202588A
公开(公告)日：1993-04-13
申请号：US827267
申请日：1992-01-29
申请人： Ryosuke Matsuo , Masaru Koyanagi
发明人： Ryosuke Matsuo , Masaru Koyanagi
IPC分类号： G11C11/413 , G05F3/20 , G11C11/408 , H01L21/822 , H01L27/04 , H02M3/07 , H03K19/094
CPC分类号： G05F3/205 , H02M3/07
摘要： There is disclosed a substrate bias circuit including an oscillation circuit oscillating at a predetermined frequency; a control signal generation circuit operative to generate a control signal for changing, on the basis of an output from the oscillation circuit, a substrate potential in a direction to ensure a threshold level of a transistor so that it becomes greater; and a charge pump circuit including a capacitor and operative to control discharge of the capacitor by said control signal to thereby change the substrate potential.
摘要翻译：公开了一种衬底偏置电路，包括以预定频率振荡的振荡电路; 控制信号生成电路，用于产生控制信号，用于根据来自振荡电路的输出，在确保晶体管的阈值电平使其变大的方向上改变衬底电位; 以及电荷泵电路，其包括电容器，并且用于通过所述控制信号控制电容器的放电，从而改变衬底电位。

30. 发明授权

US4267427A Method of boring a hole through a magnet made of an intermetallic compound 失效
标题翻译：通过由金属间化合物制成的磁体钻孔的方法
公开(公告)号：US4267427A
公开(公告)日：1981-05-12
申请号：US970951
申请日：1978-12-19
申请人： Hiroki Nomura , Masao Mafune , Masaru Koyanagi
发明人： Hiroki Nomura , Masao Mafune , Masaru Koyanagi
IPC分类号： B23K26/38 , B23K27/00
CPC分类号： B23K26/382 , B23K26/40 , B23K26/402 , B23K2201/35 , B23K2203/08 , B23K2203/26 , B23K2203/42 , B23K2203/50 , B23K2203/52 , Y10T29/49075
摘要： A method of boring a hole through a magnet made of an intermetallic compound, characterized in that the hole is formed by a laser machining. The magnet may be reinforced by impregnation with a nonmagnetic material such as a high polymeric substance or a metal having a low melting point before the hole is bored through the magnet by laser machining.
摘要翻译：通过由金属间化合物制成的磁体钻孔的方法，其特征在于，所述孔通过激光加工形成。可以通过用非磁性材料（例如高聚合物质或具有低熔点的金属）进行浸渍来增强磁体，然后通过激光加工在孔内钻孔。

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