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21. 发明申请

US20130013980A1 Data Management in Solid State Storage Devices 审中-公开
标题翻译：固态存储设备中的数据管理
公开(公告)号：US20130013980A1
公开(公告)日：2013-01-10
申请号：US13617571
申请日：2012-09-14
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： H03M13/05
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器中的输入数据的位置的元数据被保存在存储器中。还保持了存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，从该块中包含写入位置的该组或每个所述组恢复有效的输入数据。然后将恢复的数据重新存储为新的输入数据。

22. 发明申请

US20110066788A1 CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES 有权
标题翻译：用于减少固体装置中的写入放大的集装箱标记方案
公开(公告)号：US20110066788A1
公开(公告)日：2011-03-17
申请号：US12559959
申请日：2009-09-15
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G11C16/349 , G11C16/3495
摘要： A solid state storage device and method are provided. Multiple blocks are configured as storage memory for a solid state storage device, and each block includes multiple pages. A controller is configured to operate the solid state storage device. A free block of the multiple blocks is assigned a marker level by the controller. For a particular page of the multiple pages, each particular page of data is written to a block of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller for that particular page.
摘要翻译：提供了一种固态存储装置和方法。多个块被配置为固态存储设备的存储存储器，并且每个块包括多个页面。控制器被配置为操作固态存储设备。多个块的空闲块由控制器分配一个标记级别。对于多页的特定页面，每个特定的数据页面被写入多个块的块，其中标记级别对应于由该控制器为该特定页面计算的动态水平。

23. 发明授权

US09170933B2 Wear-level of cells/pages/sub-pages/blocks of a memory 有权
标题翻译：存储器的单元/页/子页/块的磨损级别
公开(公告)号：US09170933B2
公开(公告)日：2015-10-27
申请号：US13700545
申请日：2011-06-06
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Roman Pletka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Roman Pletka
IPC分类号： G06F9/312 , G06F12/02 , G11C16/34
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： A method for wear-leveling cells, pages, sub-pages or blocks of a memory such as a flash memory includes receiving (S10) a chunk of data to be written on the cell, page, sub-page or block of the memory; counting (S40), in the received chunk of data, a number of times a given type of binary data ‘0’ or ‘1’ is to be written; and distributing (S50) the writing of the received chunk of data among cells, pages, sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data ‘0’ or ‘1’ counted in the chunk of data to be written.
摘要翻译：一种用于对诸如闪速存储器的存储器的单元，页，子页或块进行磨损均衡的方法包括：接收（S10）要写入存储器的单元，页，子页或块的数据块; 在接收到的数据块中计数（S40）多少次给定类型的二进制数据“0”或“1”被写入; 并且分配（S50）在所述存储器的单元，页面，子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别 “1”计入要写入的数据块中。

24. 发明授权

US08495471B2 Solid-state storage system with parallel access of multiple flash/PCM devices 有权
标题翻译：具有并行访问多个闪存/ PCM设备的固态存储系统
公开(公告)号：US08495471B2
公开(公告)日：2013-07-23
申请号：US12627364
申请日：2009-11-30
申请人： Theodore A. Antonakopoulos , Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Theodore A. Antonakopoulos , Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G11C29/00
CPC分类号： G06F11/1028 , G11C29/765
摘要： Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.
摘要翻译：提供了通过使用容错架构以及用于随机/突发错误校正的一个纠错码（ECC）机制来解决固态驱动器（SSD）中的故障存储集成电路（IC）的问题的系统和方法，以及 L折叠交织机制。当一个或多个集成电路出现故障并且允许从故障集成电路恢复先前存储的数据并且允许在其他操作集成电路中校正随机/突发错误时，本文描述的系统和方法保持SSD的可操作性。这些系统和方法用作为备用集成电路处理的全功能/可操作集成电路来代替故障集成电路。此外，这些系统和方法在最大可实现的读/写数据速率方面提高了I / O性能。

25. 发明申请

US20130166827A1 WEAR-LEVEL OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY 有权
标题翻译：细胞/页/子页面/记忆体的层数
公开(公告)号：US20130166827A1
公开(公告)日：2013-06-27
申请号：US13700545
申请日：2011-06-06
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Roman Pletka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis , Roman Pletka
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： The invention is directed to a method for wear-leveling cells or pages or sub-pages or blocks of a memory such as a flash memory, the method comprising:—receiving (S10) a chunk of data to be written on a cell or page or sub-page or block of the memory;—counting (S40) in the received chunk of data the number of times a given type of binary data ‘0’ or ‘I’ is to be written; and—distributing (S50) the writing of the received chunk of data amongst cells or pages or sub-pages or blocks of the memory such as to wear-level the memory with respect to the number of the given type of binary data ‘0’ or ‘I’ counted in the chunk of data to be written.
摘要翻译：本发明涉及一种用于对诸如闪速存储器的存储器的单元格或页面或子页面或块进行磨损均衡的方法，所述方法包括： - 接收（S10）要写入单元或页面的数据块或存储器的子页面或块; - 在接收的数据块中记录给定类型的二进制数据“0”或“I”的次数（S40）; （S50）在存储器的单元格或页面或子页面或块之间写入所接收的数据块，以便相对于给定类型的二进制数据“0”的数量对存储器进行磨损级别或者“我”在要写入的数据块中计数。

26. 发明申请

US20120290779A1 DATA MANAGEMENT IN SOLID-STATE STORAGE DEVICES AND TIERED STORAGE SYSTEMS 审中-公开
公开(公告)号：US20120290779A1
公开(公告)日：2012-11-15
申请号：US13560635
申请日：2012-07-27
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
IPC分类号： G06F12/00
CPC分类号： G06F3/0647 , G06F3/0616 , G06F3/0652 , G06F3/0685
摘要： A method for managing data in a data storage system having a solid-state storage device and alternative storage includes identifying data to be moved in the solid-state storage device for internal management of the solid-state storage; moving at least some of the identified data to the alternative storage instead of the solid-state storage; and maintaining metadata indicating the location of data in the solid-state storage device and the alternative storage.

27. 发明授权

US09531406B2 Decoding of LDPC code 有权
标题翻译： LDPC码的解码
公开(公告)号：US09531406B2
公开(公告)日：2016-12-27
申请号：US14358609
申请日：2011-05-25
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Dung Nguyen
IPC分类号： H03M13/11 , H03M13/29
CPC分类号： H03M13/1105 , H03M13/1108 , H03M13/2957
摘要： It is provided a method for decoding a sequence of bits encoded by a LPDC code. The method comprises providing a set of bit states, including a first state and a second state, and a set of conditions to change a bit state including a first condition 5 and a second condition. The first condition and the second condition are different. The method comprises reading the value of each bit of the sequence, associating each bit to a respective state of the set according to the values as read, determining that an evaluated condition is met and changing the state of the target bit as a result of the condition being met. The method may then set the value of the target bit of the 10 sequence according to the state thereof. Such a method provides a solution for decoding a sequence of bits encoded by a LDPC code with better performance than the classic bit-flipping algorithm with only a slight increase in complexity.
摘要翻译：提供了一种用于解码由LPDC码编码的比特序列的方法。该方法包括提供一组位状态，包括第一状态和第二状态，以及一组条件以改变包括第一条件5和第二状态的位状态。第一个条件和第二个条件是不同的。该方法包括读取序列的每个比特的值，根据读取的值将每个比特与组的相应状态相关联，确定满足评估条件并改变目标比特的状态作为结果条件得到满足然后，该方法可以根据其状态设置10序列的目标比特的值。这种方法提供了一种解码方案，用于以比典型的比特翻转算法更好的性能来解码由LDPC码编码的比特序列，只有稍微增加的复杂度。

28. 发明授权

US08904261B2 Data management in solid state storage devices 有权
标题翻译：固态存储设备中的数据管理
公开(公告)号：US08904261B2
公开(公告)日：2014-12-02
申请号：US13516053
申请日：2010-12-16
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： G11C29/00 , H03M13/05 , G06F11/10
CPC分类号： G06F11/108 , G06F11/1008 , G06F11/1068 , H03M13/05
摘要： A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the each said group containing write locations in that block. The recovered data is then re-stored as new input data.
摘要翻译：提供了一种用于控制固态存储装置的机构，其中固态存储器包括每个包括多个数据写入位置的可擦除块。输入数据被存储在连续的数据写入位置组中，每个组包括在固态存储器的多个逻辑分区中的每一个中的一组可擦除块中的写入位置。输入数据被纠错编码，使得每个组包含用于该组中的输入数据的纠错码。指示固态存储器中的输入数据的位置的元数据被保存在存储器中。还保持了存储在每个数据写入位置中的数据的有效性的指示。在擦除块之前，从包含该块中的写入位置的每个所述组恢复有效的输入数据。然后将恢复的数据重新存储为新的输入数据。

29. 发明申请

US20120278544A1 FLASH MEMORY CONTROLLER 有权
标题翻译：闪存控制器
公开(公告)号：US20120278544A1
公开(公告)日：2012-11-01
申请号：US13515118
申请日：2010-12-09
申请人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
发明人： Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu
IPC分类号： G06F12/02
CPC分类号： G06F13/1668 , G06F9/3004 , G11C7/1042
摘要： A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.
摘要翻译：闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装，并通过第一闪存存储器接口耦合到第二闪存存储器封装。闪存控制器被设计为接收与第一闪存存储器包相关的第一指令，并且根据第一指令执行第一处理。闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令，并且根据第二指令执行第二处理。闪存控制器还适用于将第一进程分成至少两个第一子步骤，并将第二进程分成至少两个第二子步骤。闪存控制器还适用于执行第一和第二子步骤，并且用于交错执行第一和第二子步骤。

30. 发明申请

US20110131472A1 SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES 有权
标题翻译：具有并行访问多个闪存/ PCM设备的固态存储系统
公开(公告)号：US20110131472A1
公开(公告)日：2011-06-02
申请号：US12627364
申请日：2009-11-30
申请人： Theodore A. Antonakopoulos , Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
发明人： Theodore A. Antonakopoulos , Roy D. Cideciyan , Evangelos S. Eleftheriou , Robert Haas , Xiao-Yu Hu , Ilias Iliadis
IPC分类号： H03M13/05 , G06F11/10 , H03M13/27
CPC分类号： G06F11/1028 , G11C29/765
摘要： Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.
摘要翻译：提供了通过使用容错架构以及用于随机/突发错误校正的一个纠错码（ECC）机制来解决固态驱动器（SSD）中的故障存储集成电路（IC）的问题的系统和方法，以及 L折叠交织机制。当一个或多个集成电路出现故障并且允许从故障集成电路恢复先前存储的数据并且允许在其他操作集成电路中校正随机/突发错误时，本文描述的系统和方法保持SSD的可操作性。这些系统和方法用作为备用集成电路处理的全功能/可操作集成电路来代替故障集成电路。此外，这些系统和方法在最大可实现的读/写数据速率方面提高了I / O性能。

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