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    • 21. 发明授权
    • Buzzer mechanism for alarm clock or the like
    • 蜂鸣器机构用于闹钟等
    • US4148182A
    • 1979-04-10
    • US790985
    • 1977-04-26
    • Shuzo AbeYukio EndoYoshito Otsuki
    • Shuzo AbeYukio EndoYoshito Otsuki
    • G04C21/16G10K9/12
    • G04C21/16G10K9/12
    • A buzzer mechanism for an alarm clock or the like comprises a vibrator member rockably supported on a base plate for angular movement between an inactive position and an active position in which a vibration arm of the vibrator faces a buzzer yoke associated with the alternating driving coil of the clock so as to be vibrated. A coil spring presses the vibrator member against the base plate and also biases it toward active position. A projection on the vibrator member engages the hour wheel so that when the hour wheel is moved axially upon a projection on the hour wheel coming into registry with a hole in an unlocking drum, the vibrator member is permitted to rock to active position. An alarm stop lever is operable manually to return the vibrator member to inactive position.
    • 用于闹钟等的蜂鸣器机构包括可摆动地支撑在基板上的振动器构件,用于在非活动位置和活动位置之间进行角运动,其中振动器的振动臂面对与交替的驱动线圈相关联的蜂鸣器轭 时钟被振动。 螺旋弹簧将振动器构件压靠在基板上,并将其偏压到主动位置。 振动器构件上的突起接合小时轮,使得当小时轮在时轮上的突起与轴上的孔对准时,时轮被轴向移动时,振动器构件被允许摇摆到主动位置。 报警停止杆可手动操作以使振动器构件返回到非活动位置。
    • 22. 发明授权
    • High-speed solid-state imaging device capable of suppressing image noise
    • 能够抑制图像噪声的高速固态成像装置
    • US07292276B2
    • 2007-11-06
    • US10875780
    • 2004-06-25
    • Yoshitaka EgawaYoriko TanakaShinji OhsawaYukio EndoHiromi KusakabeNagataka Tanaka
    • Yoshitaka EgawaYoriko TanakaShinji OhsawaYukio EndoHiromi KusakabeNagataka Tanaka
    • H04N3/14
    • H04N5/3658H04N5/3575H04N5/3591H04N5/361H04N5/3698H04N5/374H04N5/3741H04N5/378
    • In a CMOS image sensor, current leakage after a series of noise removing operations has been completed is suppressed in a read operation for each horizontal line, thereby suppressing image noise occurring on the output display screen of the image sensor. There are provided signal storage regions for storing the signals read from the unit cells in the same row selected in the imaging area onto vertical signal lines and horizontal select transistors for sequentially selecting and reading the signals stored in the individual signal storage regions and transferring them to read horizontal signal lines. At least in the period during which the signals are read from the signal storage regions, one of the drain and source of the transistor electrically connected to the signal path between the vertical signal line and horizontal signal line is biased in the reverse direction with respect to the substrate region. Two adjacent ones of the horizontal select transistors form a pair. The horizontal select transistors in each pair share one of the source/drain regions so as to be connected to the horizontal signal line in common, and the others of the source/drain regions are connected to the vertical signal line individually.
    • 在CMOS图像传感器中,对于每个水平线的读取操作,抑制了一系列噪声去除操作之后的电流泄漏,从而抑制了图像传感器的输出显示屏幕上出现的图像噪声。 提供信号存储区域,用于将从成像区域中选择的同一行中的单位单元读取的信号存储到垂直信号线和水平选择晶体管上,用于顺序选择和读取存储在各个信号存储区域中的信号并将其传送到 读取水平信号线。 至少在从信号存储区读取信号的期间中,与垂直信号线和水平信号线之间的信号路径电连接的晶体管的漏极和源极之一相对于 衬底区域。 两个相邻的水平选择晶体管形成一对。 每对中的水平选择晶体管共享源极/漏极区域中的一个,以便与水平信号线共同连接,源极/漏极区域中的另一个分别连接到垂直信号线。
    • 25. 发明授权
    • Liquid crystal display device
    • US06690442B1
    • 2004-02-10
    • US09592587
    • 2000-06-12
    • Satoshi KohtakaTakafumi HashiguchiYukio Endo
    • Satoshi KohtakaTakafumi HashiguchiYukio Endo
    • G02F11343
    • G02F1/1345
    • The liquid crystal display of the present invention includes: a first insulating substrate as an array substrate; display pixels formed in such a manner as to be arranged in array like shape on the first insulating substrate, said display pixels having pixel electrodes electrically connected to each other; a counter substrate formed on a second insulating substrate on which common electrodes are formed; a liquid crystal layer interposed between the first insulating substrate and the second insulating substrate, the first insulating substrate and the second insulating substrate being bonded each other; a transfer electrode for supplying a common electrical potential to common electrodes on the second insulating substrate through a conductive material; wherein the transfer electrode is formed by patterning a conductive thin film that has been formed by the last conductive film forming process of the first insulating substrate; wherein a second conductive metal film, which has been formed in the second conductive film forming process of the first insulating substrate, and is connected to the common electrode potential, and the conductive thin film are connected to each other on the periphery of the transfer electrode through a contact hole or through a direct contact, and the conductive thin film is directly formed on the first insulating substrate at one portion of the center portion of the opening of the transfer electrode.
    • 29. 发明授权
    • Logic circuit employing flip-flop circuit
    • 采用触发电路的逻辑电路
    • US6064246A
    • 2000-05-16
    • US949558
    • 1997-10-14
    • Yukio EndoMasato Nagamatsu
    • Yukio EndoMasato Nagamatsu
    • G11C19/00G11C19/28H03K3/289
    • G11C19/00G11C19/28
    • A flip-flop circuit consists of a conventional pulse-drive flip-flop plus a clock driver and a local pulse generator that generates a pulse signal according to the output of the clock driver. The flip-flop circuits of this kind are used to form, for example, a shift register in which the clock drivers are connected in series from the last stage toward the first stage. The clock driver in the last stage receives a clock signal, which is successively supplied to the flip-flop circuits from the one in the last stage toward the one in the first stage. This arrangement prevents a data-pass-through problem, assures a sharp waveform of pulse signals, and reduces the size of each clock driver. This type of flip-flop circuits may be used to form logic circuits such as N-bit registers and N-bit shift registers.
    • 触发器电路由传统的脉冲驱动触发器加上时钟驱动器和本地脉冲发生器组成,该脉冲发生器根据时钟驱动器的输出产生脉冲信号。 这种触发器电路用于形成例如其中时钟驱动器从最后阶段到第一阶段串联连接的移位寄存器。 最后一级的时钟驱动器接收时钟信号,该时钟信号从最后阶段的触发器电路连续地提供给第一级的时钟信号。 这种安排可防止数据通过问题,确保脉冲信号的尖锐波形,并减小每个时钟驱动器的大小。 这种类型的触发器电路可以用于形成诸如N位寄存器和N位移位寄存器的逻辑电路。