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21. 发明申请

US20080191257A1 3-D Channel Field-Effect Transistor, Memory Cell and Integrated Circuit 有权
标题翻译： 3-D通道场效应晶体管，存储单元和集成电路
公开(公告)号：US20080191257A1
公开(公告)日：2008-08-14
申请号：US11674164
申请日：2007-02-13
申请人： Dietmar Temmler , Alexander Sieck
发明人： Dietmar Temmler , Alexander Sieck
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L29/7834 , H01L27/10817 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10876 , H01L27/10879 , H01L29/7835 , H01L29/7854
摘要： A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.
摘要翻译：场效应晶体管包括源极区，漏极区和源极和漏极区之间的沟道区。栅极电极也布置在它们之间，其中栅电极的下边缘形成在源极和漏极区域中的至少一个的下边缘的下方。在栅电极和源极区之间提供第一绝缘体结构。在栅极电极和漏极区域之间提供第二绝缘体结构。第一和第二绝缘体结构形成为不对称的并且可以适应于不同的要求。非对称方法可以提供更长的晶体管通道，栅电极的较低电阻以及用于例如存储器单元或电力应用中的阵列和支持晶体管的3D通道晶体管的较小占位面积。

22. 发明申请

US20080179705A1 Semiconductor device, method for manufacturing a semiconductor device and mask for manufacturing a semiconductor device 失效
标题翻译：半导体装置，半导体装置的制造方法以及半导体装置的制造掩模
公开(公告)号：US20080179705A1
公开(公告)日：2008-07-31
申请号：US11700547
申请日：2007-01-31
申请人： Christoph Noelscher , Dietmar Temmler
发明人： Christoph Noelscher , Dietmar Temmler
IPC分类号： H01L29/00 , G03F1/00 , H01L21/76
CPC分类号： H01L21/764 , G03F1/36 , H01L27/0207 , H01L27/105
摘要： A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90°. The structure and the second structure are distanced by a spacer structure.
摘要翻译：具有衬底的半导体器件包括结构。该结构具有第一部分和第二部分。结构的第一部分的边缘的至少一个部分是平行于衬底测量到第二结构的边缘的第一部分的基本恒定距离。结构的第二部分的边缘的至少一个部分衬有同一第二部分的第二部分的边缘。第二结构的边缘的第一部分和第二结构的边缘的第二部分至少在一点处合并，由此第二结构的第一和第二部分的边缘的切线之间的角度小于 90°。结构和第二结构由间隔结构隔开。

23. 发明授权

US07084029B2 Method for fabricating a hole trench storage capacitor in a semiconductor substrate, and hole trench storage capacitor 失效
标题翻译：在半导体衬底中制造空穴沟槽存储电容器的方法和空穴沟槽存储电容器
公开(公告)号：US07084029B2
公开(公告)日：2006-08-01
申请号：US10948574
申请日：2004-09-24
申请人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
发明人： Srivatsa Kundalgurki , Dietmar Temmler , Hans-Peter Moll , Joerg Wiedemann
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10867 , H01L27/10873
摘要： To fabricate a hole trench storage capacitor having an inner electrode, which is formed in a hole trench, and an outer electrode, which is formed in an electrode section, surrounding the hole trench in a lower section, of the semiconductor substrate, the inner electrode is continued above the substrate surface of the semiconductor substrate. Then, an additional layer, which widens the semiconductor substrate, is grown onto the substrate surface by an epitaxy process. A transition surface for contact-connection of the inner electrode and at least a part of an insulation collar is formed above the original substrate surface, thereby increasing the size of a surface area of the hole trench storage capacitor, which can be used for charge storage, while using the same aspect ratio for an etch used to form the hole trench.
摘要翻译：为了制造在半导体衬底中形成有形成在孔沟中的内部电极和在电极部中形成的包围下部的孔沟的外部电极的空穴沟槽存储电容器，内部电极继续在半导体衬底的衬底表面上方。然后，通过外延工艺将扩大半导体衬底的附加层生长到衬底表面上。在原始基板表面上形成内电极和绝缘套环的至少一部分的接触连接的过渡表面，从而增加可用于电荷存储的空穴沟槽存储电容器的表面积的尺寸而对于用于形成孔沟槽的蚀刻使用相同的纵横比。

24. 发明申请

US20050250290A1 Trench and a trench capacitor and method for forming the same 失效
标题翻译：沟槽和沟槽电容器及其形成方法
公开(公告)号：US20050250290A1
公开(公告)日：2005-11-10
申请号：US11108154
申请日：2005-04-15
申请人： Dietmar Temmler
发明人： Dietmar Temmler
IPC分类号： H01L21/20 , H01L21/334 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/1087 , H01L27/10829 , H01L27/10864 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： A method for fabricating a trench includes providing a semiconductor substrate made of a semiconductor material. A trench is etched into a surface of the semiconductor substrate such that a trench wall is produced. At least one layer is provided on the trench wall. This step is performed in such a way that the topmost layer provided on the trench wall is constructed from a sealing material. A selective epitaxy method is carried out in such a way that a monocrystalline semiconductor layer is formed on the surface of the semiconductor substrate and preferably no semiconductor material grows directly on the sealing material. A partial trench is etched in a surface of the epitaxially grown semiconductor layer. This step is performed in such a way that at least part of the layer made of the sealing material is uncovered. An uncovered part of the layer made of the sealing material is then removed.
摘要翻译：制造沟槽的方法包括提供由半导体材料制成的半导体衬底。将沟槽蚀刻到半导体衬底的表面中，使得产生沟槽壁。在沟槽壁上设置至少一层。该步骤以使得设置在沟槽壁上的最上层由密封材料构成的方式进行。以这样的方式进行选择性外延法，即在半导体衬底的表面上形成单晶半导体层，并且优选地，半导体材料不直接在密封材料上生长。在外延生长的半导体层的表面中蚀刻部分沟槽。该步骤以使得由密封材料制成的层的至少一部分未被覆盖的方式进行。然后除去由密封材料制成的层的未覆盖部分。

25. 发明申请

US20050148171A1 Method for filling trench and relief geometries in semiconductor structures 有权
标题翻译：在半导体结构中填充沟槽和浮雕几何的方法
公开(公告)号：US20050148171A1
公开(公告)日：2005-07-07
申请号：US11010186
申请日：2004-12-10
申请人： Dietmar Temmler , Barbara Lorenz , Daniel Koehler , Matthias Foerster
发明人： Dietmar Temmler , Barbara Lorenz , Daniel Koehler , Matthias Foerster
IPC分类号： H01L21/28 , H01L21/02 , H01L21/311 , H01L21/334 , H01L21/4763 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76877 , H01L21/31116 , H01L21/76224 , H01L21/76837 , H01L21/76843 , H01L21/76865 , H01L27/10861 , H01L27/1087 , H01L28/60 , H01L28/84 , H01L29/66181
摘要： A method teaches how to fill trench structures formed in a semiconductor substrate. The trench structures are coated in a first deposition process with a first primary filling layer with a high conformity and minimal roughness. A V etching reaching down to a predetermined depth of the trench structure is subsequently performed in order to produce a V-profile.
摘要翻译：一种方法教导了如何填充形成在半导体衬底中的沟槽结构。沟槽结构在具有高一致性和最小粗糙度的第一初级填充层的第一沉积工艺中被涂覆。随后进行达到沟槽结构的预定深度的V蚀刻，以便产生V形轮廓。

26. 发明申请

US20050079702A1 Method for producing an electrically conductive contact 失效
标题翻译：用于制造导电触头的方法
公开(公告)号：US20050079702A1
公开(公告)日：2005-04-14
申请号：US10893561
申请日：2004-07-16
申请人： Martin Popp , Dietmar Temmler
发明人： Martin Popp , Dietmar Temmler
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/76897 , H01L21/76807 , H01L21/76838 , H01L21/823425 , H01L21/823475 , H01L2221/1026
摘要： An electrically conductive contact can be used to connect an integrated component to an interconnect. A sacrificial layer is deposited on a liner and planarized until a surface of the integrated component is uncovered. The sacrificial layer is patterned to define the later contacts. The layer is covered in a partial region above contact connection regions. An interlevel insulator is deposited and patterned, so that the sacrificial layer can then be stripped out from the partial region. After the removal of the liner, a conductive layer is deposited into the cavity formed as a result of the stripping-out process on the uncovered contact connection regions and optionally into trenches formed at the outset within the interlevel insulator.
摘要翻译：可以使用导电触点将集成部件连接到互连。将牺牲层沉积在衬垫上并且平坦化，直到集成组件的表面未被覆盖。将牺牲层图案化以限定稍后的接触。该层被覆盖在接触连接区域上方的局部区域中。沉积和图案化层间绝缘体，从而可以从部分区域剥离牺牲层。在去除衬套之后，导电层沉积到由未剥离的接触连接区域上的剥离过程形成的空腔中，并且任选地沉积在层间绝缘体内的开始形成的沟槽中。

27. 发明授权

US08003538B2 Method for producing a structure on the surface of a substrate 有权
标题翻译：在基板表面上制造结构的方法
公开(公告)号：US08003538B2
公开(公告)日：2011-08-23
申请号：US12114948
申请日：2008-05-05
申请人： Christoph Nölscher , Dietmar Temmler , Peter Moll
发明人： Christoph Nölscher , Dietmar Temmler , Peter Moll
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
摘要翻译：本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。在这种情况下，第一种方法包括在衬底的表面上形成第一部分结构，其具有规则地排列并且基本相同地间隔开的结构元件。第二种方法包括在衬底的表面上形成间隔物，其邻接第一部分结构的结构元件的侧壁，在间隔物之间提供切口。第三种方法步骤包括将填充材料引入间隔件之间的切口中，间隔件的表面未被覆盖。第四种方法步骤包括去除间隔物，以便形成具有填充材料的第二部分结构，并具有规则排列的结构元件并且基本相同地间隔开。要制造的结构由第一部分结构和第二部分结构组成。

28. 发明申请

US20080206681A1 METHOD FOR PRODUCING A STRUCTURE ON THE SURFACE OF A SUBSTRATE 有权
标题翻译：生产基材表面结构的方法
公开(公告)号：US20080206681A1
公开(公告)日：2008-08-28
申请号：US12114948
申请日：2008-05-05
申请人： Christoph Nolscher , Dietmar Temmler , Peter Moll
发明人： Christoph Nolscher , Dietmar Temmler , Peter Moll
IPC分类号： G03F7/20 , H01B13/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088
摘要： The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
摘要翻译：本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。在这种情况下，第一种方法包括在衬底的表面上形成第一部分结构，其具有规则地排列并且基本相同地间隔开的结构元件。第二种方法包括在衬底的表面上形成间隔物，其邻接第一部分结构的结构元件的侧壁，在间隔物之间提供切口。第三种方法步骤包括将填充材料引入间隔件之间的切口中，间隔件的表面未被覆盖。第四种方法步骤包括去除间隔物，以便形成具有填充材料的第二部分结构，并具有规则排列的结构元件并且基本相同地间隔开。要制造的结构由第一部分结构和第二部分结构组成。

29. 发明申请

US20050199078A1 Method and apparatus for determination of the depth of depressions which are formed in a mount substrate 有权
标题翻译：用于确定在安装基板中形成的凹陷深度的方法和装置
公开(公告)号：US20050199078A1
公开(公告)日：2005-09-15
申请号：US11060571
申请日：2005-02-17
申请人： Dietmar Temmler , Peter Weidner
发明人： Dietmar Temmler , Peter Weidner
IPC分类号： G01B21/18 , G01G19/00 , G01N5/04 , G01N33/00 , H01L21/66
CPC分类号： G01B21/18 , G01G19/00 , G01N5/04
摘要： The invention relates to a method for determination of the depth of depressions which are formed in a mount substrate. According to the invention, an essentially uniform layer of a wetting agent is applied, which contains depressions, on a surface of the mount substrate, a time profile of the decrease in weight of the mount substrate is recorded, and the recorded time profile of the decrease in weight of the mount substrate is evaluated. The invention also relates to a measurement apparatus.
摘要翻译：本发明涉及一种用于确定在安装基板中形成的凹陷深度的方法。根据本发明，在安装基板的表面上施加基本上均匀的润湿剂层，其含有凹陷，记录安装基板的重量减小的时间曲线，记录时间曲线评估安装基板的重量的减小。本发明还涉及一种测量装置。

30. 发明授权

US07834395B2 3-D channel field-effect transistor, memory cell and integrated circuit 有权
标题翻译： 3-D通道场效应晶体管，存储单元和集成电路
公开(公告)号：US07834395B2
公开(公告)日：2010-11-16
申请号：US11674164
申请日：2007-02-13
申请人： Dietmar Temmler , Alexander Sieck
发明人： Dietmar Temmler , Alexander Sieck
IPC分类号： H01L27/088
CPC分类号： H01L29/7834 , H01L27/10817 , H01L27/10823 , H01L27/10826 , H01L27/10829 , H01L27/10876 , H01L27/10879 , H01L29/7835 , H01L29/7854
摘要： A field-effect transistor includes a source region, a drain region and a channel region between the source and the drain region. A gate electrode is also arranged between them, where a lower edge of the gate electrode is formed below a lower edge of at least one of the source and drain regions. A first insulator structure is provided between the gate electrode and the source region. A second insulator structure is provided between the gate electrode and the drain region. The first and the second insulator structures are formed asymmetric and may be adapted to different requirements. The asymmetric approach may provide longer transistor channels, a lower resistance of the gate electrode and smaller footprints for 3D-channel-transistors of, for example, array and support transistors in memory cells or power applications.
摘要翻译：场效应晶体管包括源极区，漏极区和源极和漏极区之间的沟道区。栅极电极也布置在它们之间，其中栅电极的下边缘形成在源极和漏极区域中的至少一个的下边缘的下方。在栅电极和源极区之间提供第一绝缘体结构。在栅极电极和漏极区域之间提供第二绝缘体结构。第一和第二绝缘体结构形成为不对称的并且可以适应于不同的要求。非对称方法可以提供更长的晶体管通道，栅电极的较低电阻以及用于例如存储器单元或电力应用中的阵列和支持晶体管的3D通道晶体管的较小占位面积。

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