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21. 发明授权

US6140177A Process of forming a semiconductor capacitor including forming a hemispherical grain statistical mask with silicon and germanium 有权
标题翻译：形成半导体电容器的工艺包括用硅和锗形成半球形晶粒统计掩模
公开(公告)号：US6140177A
公开(公告)日：2000-10-31
申请号：US242153
申请日：1999-02-09
申请人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
发明人： Herbert Schafer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/92 , Y10S438/947
摘要： For manufacturing a capacitor that is essentially suited for DRAM arrangements, column structures that form an electrode of the capacitor are etched upon employment of a statistical mask that is produced without lithographic steps by nucleus formation of Si/Ge and subsequent selective epitaxy. Structure sizes below 100 nm can be realized in the statistical mask. Surface enlargement factors up to 60 are thus achieved.
摘要翻译： PCT No.PCT / DE97 / 01408 Sec。 371日期1999年2月9日 102（e）1999年2月9日PCT PCT 1997年7月3日PCT公布。出版物WO98 / 07184 日期1998年2月19日为了制造基本上适用于DRAM布置的电容器，使用形成电容器电极的列结构被蚀刻，使用统计掩模，其通过Si / Ge的核形成并且随后选择性地产生无平版印刷步骤外延在统计掩模中可以实现小于100nm的结构尺寸。从而达到高达60的表面增大因子。

22. 发明授权

US6127220A Manufacturing method for a capacitor in an integrated storage circuit 有权
标题翻译：集成存储电路中电容器的制造方法
公开(公告)号：US6127220A
公开(公告)日：2000-10-03
申请号：US312571
申请日：1999-05-14
申请人： Gerrit Lange , Martin Franosch , Volker Lehmann , Hans Reisinger , Herbert Schafer , Reinhard Stengl , Hermann Wendt
发明人： Gerrit Lange , Martin Franosch , Volker Lehmann , Hans Reisinger , Herbert Schafer , Reinhard Stengl , Hermann Wendt
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.
摘要翻译：在载体上施加层序列，其包含由第一导电材料和第二材料制成的交替层，其中两种材料都不同于载体材料。在层序列中形成开口，其中填充有导电材料，从而产生中心支撑结构。然后根据电容器的尺寸构造层序列，并且选择性地去除由第二材料制成的层，从而形成第一电容器电极。层序列可以具有特别的p + - / p-硅层或硅/锗层。也可以将蚀刻停止层作为最低层或第二层加入。

23. 发明授权

US5943571A Method for manufacturing fine structures 失效
标题翻译：制造精细结构的方法
公开(公告)号：US5943571A
公开(公告)日：1999-08-24
申请号：US883571
申请日：1997-06-26
申请人： Herbert Schaefer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
发明人： Herbert Schaefer , Martin Franosch , Reinhard Stengl , Volker Lehmann , Hans Reisinger , Hermann Wendt
IPC分类号： C23C16/04 , H01L21/033 , H01L21/20 , H01L21/205 , H01L21/266 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , C23C16/04 , H01L21/02381 , H01L21/02425 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/0334 , H01L27/11517 , H01L29/66825
摘要： For manufacturing fine structures, nuclei that define the dimensions of the fine structures are formed on the surface of a substrate in a CVD process upon employment of a first process gas that contains SiH.sub.4 and GeH.sub.4 in a carrier gas. The nuclei can be employed both as a mask, for example, when etching or implanting, as will as active or passive component parts that remain in the structure, for example, as charge storages in the dielectric of an EEPROM.
摘要翻译：为了制造精细结构，使用在载气中使用含有SiH 4和GeH 4的第一工艺气体时，在CVD工艺的基板的表面上形成限定精细结构的尺寸的核。核可以同时用作掩模，例如蚀刻或注入时，以及保留在结构中的有源或无源部件，例如作为电荷存储在EEPROM的电介质中。

24. 发明授权

US5817553A Process for manufacturing capacitors in a solid state configuration 失效
标题翻译：用于制造固态配置的电容器的工艺
公开(公告)号：US5817553A
公开(公告)日：1998-10-06
申请号：US766977
申请日：1996-12-16
申请人： Reinhard Stengl , Martin Franosch , Hermann Wendt
发明人： Reinhard Stengl , Martin Franosch , Hermann Wendt
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： Capacitors, in particular stacked capacitors for a dynamic memory cell configuration are manufactured by first forming a sequence of layers, which include layers made of a first conductive material alternating with layers made of a second material. The second material can be selectively etched with respect to the first material. Layered structures are formed from the sequence of layers, with the flanks of the layered structures each having a conductive support structure. The layered structures are formed with openings, such as gaps, in which the surface of the layers is exposed. The layers made of the second material are selectively removed with respect to the layers made of the first material. The exposed surface of the layers made of the first material and of the support structure are provided with a capacitor dielectric, onto which a counter-electrode is placed. The capacitor is made by etching p.sup.- -doped polysilicon that is selective to p.sup.+ -doped polysilicon.
摘要翻译：制造用于动态存储单元配置的电容器，特别是用于动态存储单元配置的层叠电容器，是通过首先形成一层层而制成的，该层包括由与第二材料制成的层交替的第一导电材料制成的层。可以相对于第一材料选择性地蚀刻第二材料。层状结构由层序列形成，层状结构的侧面各自具有导电支撑结构。层状结构形成有诸如间隙的开口，其中层的表面暴露在其中。由第二材料制成的层相对于由第一材料制成的层选择性地去除。由第一材料和支撑结构制成的层的暴露表面设置有电容器电介质，其上放置有相对电极。电容器是通过蚀刻对p +掺杂多晶硅有选择性的p掺杂多晶硅制成的。

25. 发明申请

US20120025382A1 Devices Formed With Dual Damascene Process 有权
标题翻译：形成双镶嵌工艺的装置
公开(公告)号：US20120025382A1
公开(公告)日：2012-02-02
申请号：US13271878
申请日：2011-10-12
申请人： Philipp Riess , Erdem Kaltalioglu , Hermann Wendt
发明人： Philipp Riess , Erdem Kaltalioglu , Hermann Wendt
IPC分类号： H01L23/532 , H01L23/528
CPC分类号： H01L23/53238 , H01L21/31608 , H01L21/31629 , H01L21/31695 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L23/53228 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
摘要翻译：公开了在半导体部件上形成金属化层的结构和方法。该方法包括使用金属线掩模蚀刻金属线沟槽，并且在蚀刻金属线沟槽之后使用通孔掩模蚀刻通孔沟槽。通孔沟槽仅在金属线掩模和通孔掩模两者共同的区域中被蚀刻。

26. 发明授权

US07906426B2 Method of controlled low-k via etch for Cu interconnections 有权
标题翻译：用于Cu互连的受控低k通孔蚀刻的方法
公开(公告)号：US07906426B2
公开(公告)日：2011-03-15
申请号：US11788969
申请日：2007-04-23
申请人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
发明人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31138
摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.
摘要翻译：互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层蚀刻停止层。通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。灰化将ILD的这部分转化为氧化物材料。该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

27. 发明申请

US20100197112A1 Semiconductor Devices and Methods of Manufacture Thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100197112A1
公开(公告)日：2010-08-05
申请号：US12762172
申请日：2010-04-16
申请人： Armin Tilke , Frank Huebinger , Hermann Wendt
发明人： Armin Tilke , Frank Huebinger , Hermann Wendt
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and a trench formed within the workpiece. The trench has an upper portion and a lower portion, the upper portion having a first width and the lower portion having a second width, the second width being greater than the first width. A first material is disposed in the lower portion of the trench at least partially in regions where the second width of the lower portion is greater than the first width of the upper portion. A second material is disposed in the upper portion of the trench and at least in the lower portion of the trench beneath the upper portion.
摘要翻译：公开了半导体器件及其制造方法。在优选实施例中，半导体器件包括工件和形成在工件内的沟槽。沟槽具有上部和下部，上部具有第一宽度，下部具有第二宽度，第二宽度大于第一宽度。第一材料至少部分地在下部的第二宽度大于上部的第一宽度的区域中设置在沟槽的下部。第二材料设置在沟槽的上部，并且至少在上部下方的沟槽的下部。

28. 发明授权

US07452804B2 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US07452804B2
公开(公告)日：2008-11-18
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Kim Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/00
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

29. 发明申请

US20080108219A1 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US20080108219A1
公开(公告)日：2008-05-08
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

30. 发明申请

US20070042588A1 Single damascene with disposable stencil and method therefore 有权
标题翻译：具有一次性模板的单镶嵌和方法
公开(公告)号：US20070042588A1
公开(公告)日：2007-02-22
申请号：US11204982
申请日：2005-08-16
申请人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
发明人： Michael Beck , Bee Hong , Armin Tilke , Hermann Wendt
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , Y10S438/926
摘要： In a method of fabricating a semiconductor device, a liner is deposited over a conductive region of a wafer and a stencil layer is deposited over the liner. The stencil layer and the liner are etched to form a stencil pattern for a conductive layer. A second liner is deposited over exposed surfaces of the stencil pattern, and the exposed horizontal surfaces of the second liner are removed by sputtering. A low-k dielectric layer is then deposited over the wafer, and the wafer is planarized down to the stencil pattern by chemical-mechanical polishing. The stencil pattern is removed with a wet etch to form an aperture in the wafer exposing the liner and remaining portions of the second liner. Metal is deposited in the aperture, and the surface of the wafer is replanarized by chemical-mechanical polishing to produce a planar surface for additional metallization layers that may be deposited.
摘要翻译：在制造半导体器件的方法中，衬垫沉积在晶片的导电区域上，并且模板层沉积在衬垫上。蚀刻模板层和衬垫以形成用于导电层的模板图案。第二衬里沉积在模板图案的暴露表面上，并且通过溅射去除第二衬里的暴露的水平表面。然后将低k电介质层沉积在晶片上，并且通过化学机械抛光将晶片平面化到模板图案。用湿蚀刻去除模板图案，以在晶片中形成暴露衬垫和第二衬垫的剩余部分的孔。金属沉积在孔中，晶片的表面通过化学机械抛光进行再生，以产生可沉积的附加金属化层的平面。

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