专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06810474B1 Information processor 失效
标题翻译：信息处理器
公开(公告)号：US06810474B1
公开(公告)日：2004-10-26
申请号：US09623182
申请日：2000-08-29
申请人： Yoshio Miki
发明人： Yoshio Miki
IPC分类号： G06F930
CPC分类号： G06F9/383 , G06F9/30072 , G06F9/3832
摘要： In a conventional information processor that performs speculative execution of a following instruction having a data dependency, since an arithmetic and logical unit is used in performing the speculative execution and the same ALU is used again when the prediction is wrong, the frequency of use of the ALU increases. To prevent this, a history ALU for outputting a past execution result of an instruction, as it is, as an execution result of the instruction and an instruction issue circuit for issuing an instruction whose operand is the same as a past value to the history ALU are provided with an intention of omitting the actual speculative execution. A Guard cache provided in the history cache stores addresses of instructions that give low prediction accuracy, whereby any instruction whose address has been registered in the Guard cache is prevented from being registered again in the history cache.

22. 发明授权

US6064234A Logic circuit 失效
标题翻译：逻辑电路
公开(公告)号：US6064234A
公开(公告)日：2000-05-16
申请号：US134335
申请日：1998-08-14
申请人： Noboru Masuda , Yoshio Miki , Shun Kawabe
发明人： Noboru Masuda , Yoshio Miki , Shun Kawabe
IPC分类号： H03K19/0948 , H03K19/094
CPC分类号： H03K19/0948
摘要： A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.
摘要翻译：用作具有多个输入和高操作速度的选择器的逻辑电路。逻辑电路包括：第一FET，具有连接到第一电源的第一电极，连接到输出端子的第二电极和连接到中间控制节点的第三电极;以及并联连接在第二电源和输出端子。每个逻辑块包括具有与第一FET相反的导电类型的第二和第三FET，并串联连接在输出端和第二电源之间。每个逻辑块还包括与第二和第三FET具有相同导电类型的第四FET，并且具有连接到第二FET的第三电极的第三电极，连接到第三FET的第三电极的第一电极和第二FET 电极连接到中间控制节点。输出端子与第一电源之间的导通电阻降低，并且增加到输出端子的寄生电容也减小，从而允许逻辑电路以高速运行。

23. 发明授权

US6052776A Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition 失效
标题翻译：分支操作系统，其中指令排队等待，直到准备被确定完成，分支距离被认为是执行条件
公开(公告)号：US6052776A
公开(公告)日：2000-04-18
申请号：US951638
申请日：1997-10-16
申请人： Yoshio Miki , Kentaro Shimada , Makoto Hanawa
发明人： Yoshio Miki , Kentaro Shimada , Makoto Hanawa
IPC分类号： G06F9/32 , G06F9/38 , G06F15/00
CPC分类号： G06F9/30058 , G06F9/30072 , G06F9/30094 , G06F9/3804 , G06F9/3842
摘要： A method of effecting a branch operation without the need of instruction fetching is carried out according to the taken/untaken branch with respect to a program containing plural branch instructions, and the method is performed by an apparatus information processing. By detecting a branch instruction stored in an instruction buffer, determining its branch distance and branch condition, and if the branch distance is less than a predetermined positive distance, by then providing that branch condition as an execution condition for the instruction located within said predetermined distance to store in an instruction register, a series of instructions succeeding that branch instruction can be processed into a conditional instruction in the apparatus. The instructions may be continuously executed without refetching instructions, in both cases that a branch condition is taken and untaken. Also, the penalty of miss-prediction of a branch will be minimized.
摘要翻译：相对于包含多个分支指令的程序，根据取出/未读取分支执行不需要指令取出来实现分支操作的方法，并且该方法通过设备信息处理来执行。通过检测存储在指令缓冲器中的分支指令，确定其分支距离和分支条件，并且如果分支距离小于预定正距离，则通过将该分支条件提供为位于所述预定距离内的指令的执行条件为了存储在指令寄存器中，可以将该分支指令之后的一系列指令处理成装置中的条件指令。在不采用指令的情况下，可以连续执行指令，在两种情况下，分支条件被采取和取消。此外，一个分支的错失预测的惩罚将最小化。

24. 发明授权

US4137362A Pressure sensitive adhesive tapes 失效
标题翻译：压敏胶带
公开(公告)号：US4137362A
公开(公告)日：1979-01-30
申请号：US767421
申请日：1977-02-10
申请人： Yoshio Miki , Hideo Nishizawa , Yukio Suzuki
发明人： Yoshio Miki , Hideo Nishizawa , Yukio Suzuki
IPC分类号： C09J7/02 , B32B27/32
CPC分类号： C09J7/0275 , Y10S428/91 , Y10T428/266 , Y10T428/269 , Y10T428/28 , Y10T428/2839 , Y10T428/2843 , Y10T428/2848 , Y10T428/2857 , Y10T428/2878 , Y10T428/31909 , Y10T428/31913 , Y10T428/31924 , Y10T428/31928
摘要： A pressure sensitive adhesive tape comprising a backing and a pressure sensitive adhesive layer, wherein the backing is produced by stretching a long sheet composed of polypropylene as a main component in the substantially transverse direction, the backing having the properties that the shock edge tearing resistance is below 200g, the elongation at break is above 200% in the lengthwise direction, the tensile strength is above 170 kg/cm.sup.2 in the lengthwise direction and above 800kg/cm.sup.2 in the transverse direction and the impact strength is above 15kg.cm/mm.sup.2 in the lengthwise direction and above 40kg.cm/mm.sup.2 in the transverse direction, and the backing having a thickness of about 10 to 300 microns.
摘要翻译：一种压敏粘合带，其包含背衬和压敏粘合剂层，其中所述背衬通过在大致横向上拉伸由聚丙烯作为主要成分的长片材制成，所述背衬具有冲击边缘抗撕裂性为低于200g，断裂伸长率在长度方向上高于200％，拉伸强度在纵向上高于170kg / cm2，横向高于800kg / cm2，冲击强度高于15kg.cm / mm2 长度方向和横向方向上高于40kg.cm / mm2，背衬厚度为约10至300微米。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式