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21. 发明授权

US08947278B2 Single-ended to differential buffer circuit and method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs 有权
标题翻译：单端到差分缓冲电路和至少将单端输入模拟信号耦合到具有差分输入的接收电路的方法
公开(公告)号：US08947278B2
公开(公告)日：2015-02-03
申请号：US13822347
申请日：2011-09-08
申请人： Germano Nicollini , Alberto Minuti , Marco Zamprogno
发明人： Germano Nicollini , Alberto Minuti , Marco Zamprogno
IPC分类号： H03M3/00 , H03M1/12 , G11C27/02 , H03F3/45
CPC分类号： H03M1/124 , G11C27/026 , H03F3/45475 , H03F3/45986 , H03F2203/45512 , H03F2203/45536
摘要： A single-ended to differential buffer circuit is disclosed, adapted to couple at least an input analog signal to a receiving circuit. The buffer circuit comprises an output section comprising a differential amplifier having a first and a second input, a first and a second output. The buffer circuit further comprises an input section comprising a first and a second switched capacitor, each adapted to sample said input analog signal and having a first side and a second side, the first sides of the first and second switched capacitors being controllably connectable/disconnectable to/from said first and second outputs respectively. In the buffer circuit the second sides of said first and second switched capacitors are controllably connectable/disconnectable to/from said first and second inputs of the differential amplifier respectively. Moreover, in the buffer circuit the second sides of the first and second switched capacitors are controllably connectable/disconnectable to/from said second output and said first output respectively. A method for coupling at least a single-ended input analog signal to a receiving circuit with differential inputs is also disclosed.
摘要翻译：公开了适用于将至少一个输入模拟信号耦合到接收电路的单端到差分缓冲电路。缓冲电路包括输出部分，其包括具有第一和第二输入的差分放大器，第一和第二输出。缓冲电路还包括一个输入部分，它包括一个第一和第二个开关电容器，每个开关电容器适于对所述输入模拟信号进行采样并具有第一侧和第二侧，第一和第二开关电容器的第一侧是可控地可连接/可断开的分别来自所述第一和第二输出。在缓冲电路中，所述第一和第二开关电容器的第二侧分别与差分放大器的第一和第二输入端分别可控地连接/断开。此外，在缓冲电路中，第一和第二开关电容器的第二侧分别可控地与所述第二输出端和所述第一输出端连接/断开。还公开了一种用于将至少单端输入模拟信号耦合到具有差分输入的接收电路的方法。

22. 发明授权

US07425857B2 Time-delay circuit 有权
标题翻译：延时电路
公开(公告)号：US07425857B2
公开(公告)日：2008-09-16
申请号：US11055564
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Federico Garibaldi
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： A time delay logic comprises a first stage with an inverter, a capacitor connected to the input terminal of the inverter, a constant current generator and an electronic switch controlled by an input pulse. The capacitor begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. The circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter equal to the one of the first stage.
摘要翻译：时间延迟逻辑包括具有逆变器的第一级，连接到逆变器的输入端的电容器，恒定电流发生器和由输入脉冲控制的电子开关。电容器开始在输入脉冲的预定边沿充电，并将逆变器的输入端从第一电压（接地）转换到逆变器的开关阈值电压，从而在逆变器的输出端上获得具有如参照输入脉冲的预定边缘具有取决于反相器阈值的延迟时间的边缘的脉冲。电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级中的一级的反相器。

23. 发明申请

US20080036641A1 ANALOG DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20080036641A1
公开(公告)日：2008-02-14
申请号：US11832946
申请日：2007-08-02
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/804
摘要： An analog/digital converter for converting an analog signal to a digital output code includes a local digital analog converter including a segmented array. The segmented array includes upper and lower segments of conversion elements selectively operable by respective digital command codes for respectively varying, according to binary weighted contributions, the voltages of first and second common nodes and the voltage of a second common node. A logic unit generates the digital command codes for controlling the local digital/analog converter according to a successive approximation technique for producing the digital output code. The converter includes a redistributor for modifying the command codes for redistributing the modified command codes between the lower segment and the upper segment, while making use of at least one auxiliary conversion element provided in the upper segment.
摘要翻译：用于将模拟信号转换为数字输出代码的模拟/数字转换器包括具有分段阵列的本地数字模拟转换器。分段阵列包括转换元件的上段和下段，其选择性地由相应的数字命令代码操作，以分别根据二进制加权贡献来改变第一和第二公共节点的电压和第二公共节点的电压。逻辑单元根据用于产生数字输出代码的逐次逼近技术产生用于控制本地数字/模拟转换器的数字命令代码。转换器包括再分配器，用于在使用在上段中提供的至少一个辅助转换元件的同时修改用于在下段和上段之间重新分配修改的命令代码的命令代码。

24. 发明授权

US07212143B1 Circuit for selectively analog signals into digital codes 有权
标题翻译：用于将模拟信号选择成数字码的电路
公开(公告)号：US07212143B1
公开(公告)日：2007-05-01
申请号：US11336657
申请日：2006-01-20
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi , Angelo Nagari
IPC分类号： H03M1/12
CPC分类号： H03M1/1225
摘要： A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.
摘要翻译：用于选择性地将至少一个模拟信号转换成相应数字码的电路。电路包括具有多个输入的管理块，每个输入适于接收携带转换所述至少一个模拟信号的请求的相应请求信号。管理块适于基于接收到请求信号的输入来为请求信号分配优先级，并且还可操作以基于所分配的优先级来选择一个请求信号，并输出转换启动信号对应于所选择的请求信号。电路具有用于接收东一模拟信号输入的转换块，并连接到管理块以接收转换启动信号作为输入，并启动至少一个模拟信号的转换。

25. 发明授权

US07190300B2 Switched capacitance circuit and analog/digital converter including said circuit 有权
标题翻译：开关电容电路和包括所述电路的模拟/数字转换器
公开(公告)号：US07190300B2
公开(公告)日：2007-03-13
申请号：US11113954
申请日：2005-04-25
申请人： Pierangelo Confalonieri , Marco Zamprogno
发明人： Pierangelo Confalonieri , Marco Zamprogno
IPC分类号： H03M1/12
CPC分类号： G11C27/026 , G11C27/024 , H03H19/004 , H03K5/2481 , H03K5/249 , H03M1/0682 , H03M1/468
摘要： A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.
摘要翻译：一种开关电容电路，包括：开关电容部分，其能够接收信号并执行所述信号的采样，所述部分包括至少一组电容器，每个电容器的一组电容器具有连接到公共节点的端子; 至少包括连接到所述公共节点的输入端的操作级，所述操作级在所述信号的采样时间间隔期间向所述公共节点提供电流，以对所述电容器组进行充电。该电路还包括连接到所述公共节点的辅助电路，并且能够通过用于将另外的电流注入到所述公共节点中的使能信号来激活/去激活，并且在至少等于一个等待时间间隔的至少一个时间间隔期间增加提供给所述公共节点的电流所述采样间隔的分数。

26. 发明授权

US07106237B1 Low consumption and low noise analog-digital converter of the SAR type and method of employing it 有权
标题翻译： SAR型低耗低噪声模数转换器及其应用方法
公开(公告)号：US07106237B1
公开(公告)日：2006-09-12
申请号：US11097455
申请日：2005-04-01
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/462
摘要： The described converter comprises switched-capacitor quantization means for receiving an analog quantity to be converted, a register for a digital quantity corresponding to the analog quantity, a timing pulse generator and logic means capable of responding to a conversion request signal by activating the quantization means in such a way that they will carry out predetermined operations timed by the timing pulses and load in the register the digital quantity to be furnished as output. With a view to saving electric energy during the conversion and reducing the noise induced by the generator, the generator comprises means for modifying the duration and/or the frequency of the timing pulses in response to regulation signals emitted by the logic means. Also described is a method of using the converter that comprises the following phases: loading of the analog quantity in the quantization means, memorization of the loaded analog quantity and identification in the course of successive attempts in accordance with SAR technique of the bits of the digital code corresponding to the analog quantity to be converted. The duration and/or the frequency of the timing pulses are modified during at least one of the phases indicated above in response to regulation signals emitted by the logic means.
摘要翻译：所描述的转换器包括用于接收要转换的模拟量的开关电容量化装置，对应于模拟量的数字量的寄存器，定时脉冲发生器和能够通过激活量化装置来响应转换请求信号的逻辑装置以这样的方式，它们将执行由定时脉冲定时的预定操作，并且将寄存器中的负载作为输出提供的数字量。为了在转换期间节省电能并降低由发生器引起的噪声，发生器包括用于响应于由逻辑装置发出的调节信号而修改定时脉冲的持续时间和/或频率的装置。还描述了一种使用该转换器的方法，该转换器包括以下阶段：在量化装置中加载模拟量，根据数字位的SAR技术在连续尝试过程中记录加载的模拟量和识别对应于要转换的模拟量的代码。响应于由逻辑装置发出的调节信号，定时脉冲的持续时间和/或频率在上述指示的至少一个期间被修改。

27. 发明申请

US20050231293A1 Clock-pulse generator circuit 失效
标题翻译：时钟脉冲发生器电路
公开(公告)号：US20050231293A1
公开(公告)日：2005-10-20
申请号：US11055539
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03B1/00 , H03H11/26 , H03K5/00 , H03K5/04 , H03K5/13
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译：电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路，连接到第一和第二振荡器的公共输出端的输出端子。第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。

28. 发明授权

US06686865B2 High resolution, high speed, low power switched capacitor analog to digital converter 有权
标题翻译：高分辨率，高速度，低功耗开关电容模拟数字转换器
公开(公告)号：US06686865B2
公开(公告)日：2004-02-03
申请号：US10455894
申请日：2003-06-06
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03M112
CPC分类号： H03M1/68 , H03M1/468 , H03M1/804
摘要： An analog to digital converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of a first reference voltage terminal and an input terminal. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first reference voltage terminal and the input terminal. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
摘要翻译：模数转换器包括具有相应的二进制加权电容器的第一和第二阵列的第一和第二转换器段。第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一参考电压端子和输入端子之一的第二电极。第二段的每个电容器具有连接到第二公共节点的第一电极和通过相应开关连接到第一参考电压端子和输入端子之一的第二电极。该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2
-1）.C-CATT = 2·C，其中p是在第一转换器段，C为单位电容。

29. 发明授权

US07742893B2 Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance 有权
标题翻译：用于校准具有取决于所述电容的时间常数的集成电路的可调电容的校准电路
公开(公告)号：US07742893B2
公开(公告)日：2010-06-22
申请号：US12035308
申请日：2008-02-21
申请人： Pierangelo Confalonieri , Riccardo Martignone , Marco Zamprogno
发明人： Pierangelo Confalonieri , Riccardo Martignone , Marco Zamprogno
IPC分类号： G01R35/00
CPC分类号： H03H1/02 , H03H7/0153 , H03H2210/021 , H03H2210/025 , H03H2210/036 , H03H2210/043
摘要： A calibration circuit calibrates an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance. The calibration circuit outputs a calibration signal carrying information for calibrating the capacitor and includes a calibration loop. The calibration circuit includes: a controllable capacitance unit suitable to receive a control signal and including at least one array of switched capacitors that can be activated by the control signal, the unit being such as to output a first signal characterized by a parameter depending on the amount of capacitance of the array activated by the control signal; a comparison unit suitable to receive the first signal to assess whether the parameter meets a preset condition and to output a comparison signal representative of the assessment result; a control and timing logic unit suitable to receive the comparison signal to change this control signal based on the comparison signal, characterized in that the first signal is a logic signal and the parameter is a time parameter of the first signal.
摘要翻译：校准电路根据可调电容校准具有时间常数的电路的可调电容。校准电路输出一个载有用于校准电容器的信息的校准信号，并包括校准环路。所述校准电路包括：可控电容单元，其适于接收控制信号并且包括可被所述控制信号激活的至少一个开关电容阵列，所述单元使得输出第一信号，所述第一信号的特征在于根据由控制信号激活的阵列的电容量; 适于接收第一信号以评估参数是否满足预置条件并输出表示评估结果的比较信号的比较单元; 适于接收比较信号以根据比较信号改变该控制信号的控制和定时逻辑单元，其特征在于，第一信号是逻辑信号，该参数是第一信号的时间参数。

30. 发明授权

US07283005B2 Clock-pulse generator circuit 失效
标题翻译：时钟脉冲发生器电路
公开(公告)号：US07283005B2
公开(公告)日：2007-10-16
申请号：US11055539
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03K3/03
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译：电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路，连接到第一和第二振荡器的公共输出端的输出端子。第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。

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