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    • 21. 发明授权
    • Regulating circuit for a substrate bias voltage generator
    • 衬底偏置电压发生器的调节电路
    • US5327072A
    • 1994-07-05
    • US839787
    • 1992-02-21
    • Dominique SavignacManfred MenkeDieter Gleis
    • Dominique SavignacManfred MenkeDieter Gleis
    • G06F15/78G05F3/20G11C5/14G11C11/407G11C11/408G11C11/413G05F3/16H03L1/00
    • G05F3/205G11C5/146
    • A regulating circuit for a substrate bias voltage generator for generating a substrate bias voltage in an integrated semiconductor circuit includes a Schmitt trigger circuit disposed between a first potential and a second potential of a semiconductor circuit. The Schmitt trigger circuit has an output side and an input for controlling a hysteresis function of the Schmitt trigger circuit. An inverter array is connected downstream of the output side of the Schmitt trigger circuit. The inverter array is connected to the first potential and to a first supply potential of the semiconductor circuit in terms of supply voltage, and the inverter array has an output. The input of the Schmitt trigger circuit for controlling the hysteresis function of the Schmitt trigger circuit is connected to the output of the inverter array.
    • 用于在集成半导体电路中产生衬底偏置电压的衬底偏置电压发生器的调节电路包括设置在半导体电路的第一电位和第二电位之间的施密特触发电路。 施密特触发电路具有输出端和用于控制施密特触发电路的滞后功能的输入端。 逆变器阵列连接在施密特触发电路输出侧的下游。 逆变器阵列在电源电压方面连接到半导体电路的第一电位和第一电源电位,并且逆变器阵列具有输出。 用于控制施密特触发电路的滞后功能的施密特触发电路的输入连接到逆变器阵列的输出。
    • 22. 发明授权
    • Integrated circuit and method for generating a ready signal
    • 用于产生就绪信号的集成电路和方法
    • US07463074B2
    • 2008-12-09
    • US11032536
    • 2005-01-10
    • Manfred Menke
    • Manfred Menke
    • H03L7/00
    • H03K17/22G01R19/16552
    • An integrated circuit comprises an input for receiving a supply voltage, a field-effect transistor with a gate which is connected to the input in such a manner that the gate voltage present at the gate is a function of the supply voltage, a voltage source for generating a reference voltage which is connected to the input for receiving the supply voltage, a device for determining whether the gate voltage of the field effect transistor exceeds a turn-on voltage of the field-effect transistor, and a device for generating a ready signal which indicates that the supply voltage is high enough for performing functions of the integrated circuit, the device for generating being constructed for generating the ready signal when the gate voltage of the field-effect transistor exceeds the turn-on voltage of the field-effect transistor. The integrated circuit is characterized by the fact that a device for detecting the reference voltage generated by the voltage source is provided and the device for generating the ready signal is also constructed for generating the ready signal only when the reference voltage lies within a predetermined interval.
    • 集成电路包括用于接收电源电压的输入端,具有栅极的场效应晶体管,栅极连接到输入端,使得存在于栅极的栅极电压是电源电压的函数;电压源, 产生连接到用于接收电源电压的输入的参考电压,用于确定场效应晶体管的栅极电压是否超过场效应晶体管的接通电压的装置,以及用于产生就绪信号的装置 其指示电源电压足够高以用于执行集成电路的功能,当场效应晶体管的栅极电压超过场效应晶体管的接通电压时,用于产生的器件被构造用于产生就绪信号 。 集成电路的特征在于,提供用于检测由电压源产生的参考电压的装置,并且用于产生就绪信号的装置也被构造用于仅在参考电压处于预定间隔内时才产生就绪信号。
    • 23. 发明授权
    • Semiconductor memory chip
    • 半导体存储芯片
    • US07221615B2
    • 2007-05-22
    • US11242150
    • 2005-10-04
    • Paul WallnerMartin StreiblManfred MenkeYukio FukuzoChristian SichertPeter Gregorius
    • Paul WallnerMartin StreiblManfred MenkeYukio FukuzoChristian SichertPeter Gregorius
    • G11C7/00G11C8/00
    • G11C7/1006G11C11/4096
    • A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.
    • 半导体存储器芯片包括:接收接口部分,用于以串行信号帧的形式接收外部数据,命令和地址信号; 中间数据缓冲器,用于中间存储写入数据,以及可选地写入要写入存储单元阵列的数据屏蔽位; 具有存储体组织的存储单元阵列的存储器核心; 解码器部分,用于对从接收接口部分接收的信号帧导出的地址进行解码,用于根据在一个或多个接收信号中的写入/读取命令向/从存储器单元阵列的一个或多个存储器组写入/读取数据 框架 以及帧解码器,被设置为在接收接口部分和存储器核心之间的接口,用于解码包括在一个或多个帧中的一个或多个命令,并将数据地址,命令和读/写访问指示信号输出到存储器核心 中间数据缓冲区。
    • 25. 发明申请
    • Integrated charge pump
    • 集成电荷泵
    • US20060170485A1
    • 2006-08-03
    • US11318059
    • 2005-12-19
    • Manfred Menke
    • Manfred Menke
    • G05F1/10
    • H02M3/07
    • An integrated charge pump is provided, comprising: a pump capacitor having a first terminal and a second terminal; a control unit, which operates the charge pump in an alternation between a first phase and a second phase; a first switching device in order to charge the pump capacitor with a pump voltage in the first phase; a second switching device in order to pull the potential of the first terminal to a predetermined potential in the second phase, and in order to connect the second terminal of the pump capacitor to an output node, the second switching device having a first transistor in order to connect the second terminal of the pump capacitor to the output node, a substrate terminal of the first transistor being fixedly connected to the output node; and the second switching device pulling the first terminal to the predetermined potential with a gradient, the gradient being chosen such that at no point in time is a diode breakdown voltage exceeded in the first transistor.
    • 提供了一种集成电荷泵,包括:具有第一端子和第二端子的泵电容器; 控制单元,其在第一阶段和第二阶段之间交替地操作所述电荷泵; 第一开关装置,用于在第一相中以泵浦电压对泵电容器充电; 第二开关装置,以便将第一端子的电位拉到第二相中的预定电位,并且为了将泵电容器的第二端子连接到输出节点,第二开关装置按顺序具有第一晶体管 将泵电容器的第二端子连接到输出节点,第一晶体管的基板端子固定地连接到输出节点; 并且所述第二开关器件以梯度将所述第一端子拉到所述预定电位,所述梯度被选择为使得在任何时间点都不是在所述第一晶体管中超过二极管击穿电压。
    • 26. 发明授权
    • Sleeve nut
    • 袖子螺母
    • US6053680A
    • 2000-04-25
    • US249975
    • 1999-02-12
    • Manfred Menke
    • Manfred Menke
    • F16B37/04F16B37/12F16B39/10
    • F16B37/041
    • A sleeve nut includes a nut (1) and a screw like sleeve (2) screwed into that nut, thereby fixing the sleeve nut to a component (7) of e.g. an aircraft, a car or the like. Between the component (7) and the nut (1) a socle (3) is inserted having at least one upright tongue (22). This socle (3) is locked against rotation with respect to the component (7). Furthermore the nut (1) is positively locked against rotation at the socle (3) by flats (21) or edges there-between respectively with the tongue (22) of the socle (3).
    • 套筒螺母包括螺母(1)和拧入该螺母中的螺丝状套筒(2),从而将套筒螺母固定到例如一个部件(7)上。 飞机,汽车等。 在部件(7)和螺母(1)之间,插入具有至少一个直立舌(22)的一个(3)。 该肩部(3)相对于部件(7)被锁定以防旋转。 此外,螺母(1)通过平面(21)或其边缘处于与肩部(3)的舌部(22)分别与肩部(3)旋转。