专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5731716A Programmable multibit register for coincidence and jump operations and coincidence fuse cell 失效
标题翻译：可编程多位寄存器，用于符合和跳转操作和符合保险丝单元
公开(公告)号：US5731716A
公开(公告)日：1998-03-24
申请号：US592122
申请日：1996-01-26
申请人： Luigi Pascucci
发明人： Luigi Pascucci
IPC分类号： G11C11/56 , G11C15/00 , G11C15/04 , G11C16/04 , G11C29/00 , G11C29/04 , H03K19/177
CPC分类号： G11C29/781 , G11C11/56 , G11C15/00 , G11C16/0441
摘要： A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.
摘要翻译：由多个这样的单元组成的可编程单元和多位寄存器，专门用于执行永久记录在单元或单元中的某个代码与存在于一对或多对控制线上的逻辑配置之间的一致性检查，披露每个单元有两个分支以OR配置连接到单元或多位寄存器的公共感测线。通过一对线对每个单元，即单元格的两个分支，以互补的形式应用待测试的逻辑状态。在其一个或另一个分支中永久编程的每个单元本质地执行其永久编程逻辑配置与与其相关联的补充控制线的配置之间的比较。在冗余或重新配置系统的整体电路中实现了很大的简化。

22. 发明授权

US5708601A Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device 失效
标题翻译：用于检查半导体存储器件中冗余存储元件的利用率的集成电路
公开(公告)号：US5708601A
公开(公告)日：1998-01-13
申请号：US602237
申请日：1996-02-16
申请人： Vernon G. McKenny , Luigi Pascucci , Marco Maccarrone
发明人： Vernon G. McKenny , Luigi Pascucci , Marco Maccarrone
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/835
摘要： An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.
摘要翻译：一种装置识别被选择来替换与数据总线通信的存储器矩阵的有缺陷的存储单元的冗余存储单元。冗余地址寄存器与冗余存储单元之一相关联。冗余地址寄存器存储默认状态，直到用一个缺陷存储单元的地址编程为止。控制电路在识别模式期间产生测试信号。检测电路耦合到控制电路和冗余地址寄存器，并且当冗余地址寄存器包含默认状态时，响应于测试信号产生默认检测信号。耦合到冗余单元选择电路，数据总线和控制电路的数据总线复用器响应于测试信号将默认检测信号耦合到数据总线。

23. 发明授权

US5541884A Method and circuit for suppressing data loading noise in nonvolatile memories 失效
标题翻译：用于抑制非易失性存储器中的数据加载噪声的方法和电路
公开(公告)号：US5541884A
公开(公告)日：1996-07-30
申请号：US391147
申请日：1995-02-21
申请人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
发明人： Luigi Pascucci , Carla M. Golla , Marco Maccarrone , Marco Olivo
IPC分类号： G11C11/413 , G11C7/00 , G11C7/02 , G11C7/10 , G11C7/22 , G11C16/06 , G11C16/32 , G11C17/00
CPC分类号： G11C7/02 , G11C16/32 , G11C7/1006 , G11C7/22
摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.
摘要翻译：在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。相同的信号也阻塞地址总线上的地址放大单元。

24. 发明授权

US5321317A Zero-consumption power-on reset circuit 失效
标题翻译：零消耗上电复位电路
公开(公告)号：US5321317A
公开(公告)日：1994-06-14
申请号：US936857
申请日：1992-08-27
申请人： Luigi Pascucci , Marco Olivo
发明人： Luigi Pascucci , Marco Olivo
IPC分类号： G06F1/24 , H03K17/00 , H03K17/22 , G05F1/46
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.
摘要翻译：可以与CMOS集成电路一起使用的上电复位电路包括第一和第二串联连接的反相器，其中第二反相器的输出提供复位信号。具有两个串联二极管的一系列开关和偏置线与逆变器一体地布置。采用与地的电容耦合和电源电压来防止电源电压轨之间的任何静态电流路径。该电路提供短暂的复位信号，该信号跟随电源电压，对电源电压轨上的回弹信号和内部和外部噪声都不敏感。

25. 发明授权

US4933827A Regulation of the output voltage of a voltage multiplier 失效
标题翻译：调节电压倍增器的输出电压
公开(公告)号：US4933827A
公开(公告)日：1990-06-12
申请号：US376267
申请日：1989-07-06
申请人： Marco Olivo , Luigi Pascucci , Corrado Villa
发明人： Marco Olivo , Luigi Pascucci , Corrado Villa
IPC分类号： H01L27/04 , G11C5/14 , G11C16/30 , H01L21/822 , H02M3/07
CPC分类号： G11C5/145 , G11C16/30 , H02M3/073
摘要： The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

26. 发明授权

US08824205B2 Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor 有权
公开(公告)号：US08824205B2
公开(公告)日：2014-09-02
申请号：US11279385
申请日：2006-04-11
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C5/06 , G11C7/02 , G11C16/04 , G11C16/06 , G11C16/24 , G11C8/14 , G11C8/12 , G11C7/18 , G11C7/12
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

27. 发明授权

US08630115B2 Non-volatile electronic memory device with NAND structure being monolithically integrated on semiconductor 有权
标题翻译：具有NAND结构的非易失性电子存储器件单片集成在半导体上
公开(公告)号：US08630115B2
公开(公告)日：2014-01-14
申请号：US13198978
申请日：2011-08-05
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/24 , G11C16/08 , G11C16/06 , G11C16/04 , G11C5/06 , G11C7/02
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

28. 发明申请

US20110286269A1 Non-Volatile Electronic Memory Device With NAND Structure Being Monolithically Integrated On Semiconductor 有权
标题翻译：具有NAND结构的非易失性电子存储器件集成在半导体上
公开(公告)号：US20110286269A1
公开(公告)日：2011-11-24
申请号：US13198978
申请日：2011-08-05
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/08 , H01S4/00
CPC分类号： G11C16/08 , G11C16/0408 , G11C16/0483 , G11C16/12 , G11C16/24 , Y10T29/49002
摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.
摘要翻译：非易失性电子存储器件被集成在半导体上，并且是具有NAND架构的闪存EEPROM类型，其包括至少一个分为物理扇区的存储器矩阵，其被设计为最小的可擦除单元，并且被组织成行或字线和列，或者位线的存储单元。给定物理扇区的至少一行或字线电连接到相邻物理扇区的至少一行或字线，以形成可擦除的单个逻辑扇区，其中一对连接的相应小区的源终端行指向源行的相同选择行。

29. 发明授权

US07649778B2 Method for accessing in reading, writing and programming to a NAND non-volatile memory electronic device monolithically integrated on semiconductor 有权
标题翻译：用于访问在单片集成在半导体上的NAND非易失性存储器电子器件的读取，写入和编程的方法
公开(公告)号：US07649778B2
公开(公告)日：2010-01-19
申请号：US12409740
申请日：2009-03-24
申请人： Luigi Pascucci , Paolo Rolandi
发明人： Luigi Pascucci , Paolo Rolandi
IPC分类号： G11C16/04
CPC分类号： G11C5/066 , G11C7/1018 , G11C7/1045 , G11C16/0483 , G11C16/08 , G11C2207/105
摘要： A method for accessing, in reading, programming, and erasing a semiconductor-integrated non-volatile memory device of the Flash EEPROM type with a NAND architecture having at least one memory matrix organized in rows or word lines and columns or bit lines, and wherein, for the memory, a plurality of additional address pins are provided. The method provides both an access protocol of the asynchronous type and a protocol of the extended type allowing to address, directly and in parallel, a memory extended portion by loading an address register associated with the additional pins in two successive clock pulses. A third multi-sequential access mode and a parallel additional bus referring to the additional address pins are also provided to allow a double addressing mode, sequential and in parallel.
摘要翻译：一种用于以具有至少一个以行或字线和列或位线组织的存储矩阵的NAND架构来访问，读取，编程和擦除闪存EEPROM类型的半导体集成非易失性存储器件的方法，其中为了存储器，提供了多个附加的地址引脚。该方法提供异步类型的访问协议和扩展类型的协议，允许通过在两个连续的时钟脉冲中加载与附加引脚相关联的地址寄存器来直接和并行地寻址存储器扩展部分。还提供了第三个多次访问模式和引用附加地址引脚的并行附加总线，以允许双寻址模式，顺序和并行。

30. 发明申请

US20090256248A1 CONFIGURATION TERMINAL FOR INTEGRATED DEVICES AND METHOD FOR CONFIGURING AN INTEGRATED DEVICE 有权
标题翻译：用于集成设备的配置终端和用于配置集成设备的方法
公开(公告)号：US20090256248A1
公开(公告)日：2009-10-15
申请号：US12401464
申请日：2009-03-10
申请人： Luigi Pascucci
发明人： Luigi Pascucci
IPC分类号： H01L23/52 , H01L23/498 , H01L23/522 , H01L21/50
CPC分类号： H01L23/50 , H01L23/525 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.
摘要翻译：用于集成器件的配置端子包括结构独立并连接到相应的第一和第二端子的第一和第二部分，并且其具有适合于选择性地连接到这样的第一和第二端子的至少一个接触端子。此外，一种方法构成了包括多个地址焊盘和相应的电源引脚的集成器件。该方法包括：实现至少一个配置终端，其具有在结构上独立且连接到至少一个接触终端的第一和第二部分; 提供这样的第一和第二部分与相应的端子的接触; 以及通过所述接触端子与至少一个所述端子的短路来配置所述装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式