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21. 发明授权

US07348648B2 Interconnect structure with a barrier-redundancy feature 有权
标题翻译：互连结构与屏障冗余功能
公开(公告)号：US07348648B2
公开(公告)日：2008-03-25
申请号：US11308220
申请日：2006-03-13
申请人： Chih-Chao Yang , Louis L. Hsu
发明人： Chih-Chao Yang , Louis L. Hsu
IPC分类号： H01L27/14
CPC分类号： H01L21/76849 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure that includes a barrier-redundancy feature which is capable of avoiding a sudden open circuit after an electromigration (EM) failure as well as a method of forming the same are provided. In accordance with the present invention, the barrier-redundancy feature is located within preselected locations within the interconnect structure including in a wide line region, a thin line region or any combination thereof. The barrier-redundancy feature includes an electrical conductive material located between, and in contact with, a conductive line diffusion barrier of a conductive line and a via diffusion barrier of an overlying via. The presence of the inventive barrier-redundancy feature creates an electrical path between the via diffusion barrier along the sidewalls of the via and the conductive line diffusion barrier along the sidewalls of the conductive line. This electrical path generated by the inventive barrier-redundancy feature can avoid a sudden open circuit resulting from EM failure at the bottom of the via. The presence of the inventive barrier-redundancy feature within an interconnect structure provides sufficient time for chip replacement or system operation.
摘要翻译：提供一种互连结构，其包括能够在电迁移（EM）故障之后避免突然断路的障碍物冗余特征以及其形成方法。根据本发明，阻挡冗余特征位于互连结构内的预选位置，包括在宽线区域，细线区域或其任何组合中。阻挡层冗余特征包括导电材料，其位于导电线的导电线扩散阻挡层和上覆通孔的通孔扩散阻挡层之间并与之接触。本发明的阻挡 - 冗余特征的存在在沿着导电线的侧壁的通孔的侧壁和导电线扩散阻挡层之间形成通路扩散阻挡层之间的电路径。由本发明的障碍物冗余特征产生的该电路径可以避免由于通孔底部的EM故障导致的突然开路。在互连结构内部存在本发明的障碍物冗余特征为芯片更换或系统操作提供足够的时间。

22. 发明授权

US07115921B2 Nano-scaled gate structure with self-interconnect capabilities 失效
标题翻译：具有自相互连接能力的纳米级栅极结构
公开(公告)号：US07115921B2
公开(公告)日：2006-10-03
申请号：US10930989
申请日：2004-08-31
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/80 , H01L29/76 , H01L21/337 , H01L21/336
CPC分类号： H01L21/28114 , H01L21/76895 , H01L21/823425 , H01L21/823437 , H01L21/823475 , H01L27/0629 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545
摘要： Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.
摘要翻译：集成电路上的栅极导体形成有用于将栅极导体与其它器件电连接的较大的上部。半导体器件包括具有扩大上部的栅极导体，该栅极导体将栅极导体电连接到局部扩散区。另一个半导体器件包括两个栅极导体，其具有扩大的上部，其合并以产生电互连的栅极导体。还描述和要求保护形成上述半导体器件的方法。

23. 发明授权

US08772156B2 Methods of fabricating interconnect structures containing various capping materials for electrical fuse and other related applications 有权
标题翻译：制造包含用于电熔丝和其他相关应用的各种封盖材料的互连结构的方法
公开(公告)号：US08772156B2
公开(公告)日：2014-07-08
申请号：US12118161
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L21/76825 , H01L21/76849 , H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.
摘要翻译：提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

24. 发明授权

US08558384B2 Interconnect structure containing various capping materials for electrical fuse and other related applications 有权
标题翻译：互连结构，包含用于电熔丝和其他相关应用的各种封盖材料
公开(公告)号：US08558384B2
公开(公告)日：2013-10-15
申请号：US13537879
申请日：2012-06-29
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

25. 发明授权

US07956466B2 Structure for interconnect structure containing various capping materials for electrical fuse and other related applications 有权
标题翻译：包含用于电熔丝和其他相关应用的各种封盖材料的互连结构的结构
公开(公告)号：US07956466B2
公开(公告)日：2011-06-07
申请号：US12118186
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

26. 发明申请

US20090278228A1 DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS 有权
标题翻译：用于电气保险丝和其他相关应用的各种封装材料的互连结构设计结构
公开(公告)号：US20090278228A1
公开(公告)日：2009-11-12
申请号：US12118186
申请日：2008-05-09
申请人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
发明人： Louis L. Hsu , William R. Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76829 , H01L21/76838 , H01L21/76849 , H01L23/53223 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.
摘要翻译：为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。第二互连结构具有与第一界面结构不同的第二界面结构。

27. 发明申请

US20080296728A1 SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS 失效
标题翻译：用于保险丝和抗 - 保险丝应用的半导体结构
公开(公告)号：US20080296728A1
公开(公告)日：2008-12-04
申请号：US11755995
申请日：2007-05-31
申请人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
发明人： Chih-Chao Yang , Daniel C. Edelstein , Jack A. Mandelman , Louis L. Hsu
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier.
摘要翻译：提供了一种保险丝/反熔丝结构，其中抗熔丝的编程由邻近熔丝元件形成的电动诱发小丘引起。小丘破裂位于熔丝元件的侧壁上的薄的扩散阻挡层，并且熔丝元件内的导电材料扩散到相邻的介电材料中。保险丝元件包括位于线路开口内的导电材料，该导电材料包括具有第一厚度的第一扩散阻挡层，位于侧壁上的第一厚度和线路开口的底壁。抗熔丝元件包括位于组合的通孔和线路开口内的导电材料，其包括位于组合的通路和线路开口的侧壁上的第一扩散阻挡层和具有大于第二扩散阻挡层的第二厚度的第二扩散阻挡层第一厚度位于第一扩散阻挡层上。

28. 发明授权

US07283410B2 Real-time adaptive SRAM array for high SEU immunity 有权
标题翻译：实时自适应SRAM阵列，具有高SEU抗扰度
公开(公告)号：US07283410B2
公开(公告)日：2007-10-16
申请号：US11308215
申请日：2006-03-13
申请人： Louis L. Hsu , Jack A. Mandelman , Robert C. Wong , Chih-Chao Yang
发明人： Louis L. Hsu , Jack A. Mandelman , Robert C. Wong , Chih-Chao Yang
IPC分类号： G11C7/00
CPC分类号： G11C11/4125
摘要： A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array. The accelerated fail rate data is input to an algorithm implemented for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment. The predetermined fail rate is maintained on a real-time basis in order to provide immunity to SEU consistent with optimum performance.
摘要翻译：一种用于自动调整存储器件（例如SRAM阵列）中的一个或多个电参数的系统和方法。该系统和方法实现SRAM感测子阵列，用于加速收集故障率数据，用于确定单个事件不起作息和主SRAM阵列性能之间的最佳权衡的操作点。将加速失败率数据输入到在电离粒子环境中将初级SRAM存储器阵列的SEU灵敏度设定为预定故障率的算法。为了提供符合最佳性能的SEU的免疫力，实时地维持预定的故障率。

29. 发明授权

US08450205B2 Redundancy design with electro-migration immunity and method of manufacture 失效
标题翻译：具有电迁移免疫力的冗余设计和制造方法
公开(公告)号：US08450205B2
公开(公告)日：2013-05-28
申请号：US13474244
申请日：2012-05-17
申请人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
发明人： Louis L. Hsu , Conal E. Murray , Ping-Chuan Wang , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76838 , H01L21/76847 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.
摘要翻译：提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。一种结构包括层间电线之间的交叉处的通孔簇结构。通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。

30. 发明授权

US08188786B2 Modularized three-dimensional capacitor array 有权
标题翻译：模块化三维电容阵列
公开(公告)号：US08188786B2
公开(公告)日：2012-05-29
申请号：US12565802
申请日：2009-09-24
申请人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
发明人： Louis L. Hsu , Xu Ouyang , Chih-Chao Yang
IPC分类号： H01G4/38 , H03K17/16
CPC分类号： H01L28/40 , H01L22/14 , H01L22/22 , H01L22/34 , H01L23/5223 , H01L27/0688 , H01L27/0805 , H01L28/60 , H01L2924/0002 , Y10T307/865 , H01L2924/00
摘要： A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.
摘要翻译：模块化电容器阵列包括多个电容器模块。每个电容器模块包括电容器和被配置为电气断开电容器的开关装置。开关装置包括：感测单元，被配置为检测电容器的泄漏电平，使得如果泄漏电流超过预定电平，则开关装置电连接电容器。每个电容器模块可以包括单个电容器板，两个电容器板或多于两个的电容器板。泄漏传感器和开关装置用于电气断开任何电容器阵列的电容器模块，从而保护电容器阵列免于漏电。

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