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21. 发明申请

US20070101938A1 Inductively coupled plasma processing apparatus having internal linear antenna for large area processing 审中-公开
标题翻译：具有用于大面积处理的内部线性天线的感应耦合等离子体处理装置
公开(公告)号：US20070101938A1
公开(公告)日：2007-05-10
申请号：US11643664
申请日：2006-12-22
申请人： Geun-Young Yeom , Young-Joon Lee , Kyoung-Nam Kim
发明人： Geun-Young Yeom , Young-Joon Lee , Kyoung-Nam Kim
IPC分类号： C23F1/00 , C23C16/00
CPC分类号： H01J37/321
摘要： An inductively coupled plasma processing apparatus for a large area processing, the inductively coupled plasma processing apparatus comprising: a reaction chamber; a plurality of linear antennas horizontally arranged at an inner upper portion of the reaction chamber while being spaced from each other by a predetermined distance for receiving induced RF power, the linear antennas being coupled to each other at an outer portion of the reaction chamber, the linear antennas including at least one bending antenna formed by connecting first ends of adjacent antennas, which are exposed to the outer portion of the reaction chamber, to each other; and at least one magnet positioned adjacent to the linear antennas for creating a magnetic field perpendicularly crossing an electric field created by the linear antennas in such a manner that electrons perform a spiral movement.
摘要翻译：一种用于大面积处理的电感耦合等离子体处理装置，所述电感耦合等离子体处理装置包括：反应室; 水平地布置在反应室的内部上部的多个线性天线，同时彼此隔开预定距离以接收感应RF功率，线性天线在反应室的外部彼此耦合，线性天线，其包括通过将暴露于反应室的外部的相邻天线的第一端连接而形成的至少一个弯曲天线; 以及邻近线性天线定位的至少一个磁体，用于产生垂直于由线性天线产生的电场的磁场，使得电子执行螺旋运动。

22. 发明申请

US20070070715A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070070715A1
公开(公告)日：2007-03-29
申请号：US11478123
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/10
CPC分类号： G11C7/20 , G11C7/1039
摘要： A semiconductor memory device includes a pipe latch unit having a plurality of pipe latches for latching data. An input controller controls input timing of data transmitted from data line to the pipe latch unit. An output controller controls output timing of data latched in the pipe latch unit. An initialization controller controls the input controller and the output controller to thereby initialize the pipe latch unit in response to a read/write flag signal which is activated during a write operation.
摘要翻译：一种半导体存储器件包括具有用于锁存数据的多个管道锁存器的管道锁存单元。输入控制器控制从数据线发送到管道锁存单元的数据的输入定时。输出控制器控制锁存在管道锁存单元中的数据的输出定时。初始化控制器控制输入控制器和输出控制器，从而响应于在写操作期间被激活的读/写标志信号来初始化管锁存单元。

23. 发明授权

US08059483B2 Address receiving circuit for a semiconductor apparatus 有权
标题翻译：半导体装置的地址接收电路
公开(公告)号：US08059483B2
公开(公告)日：2011-11-15
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

24. 发明授权

US07830188B2 Semiconductor integrated circuit and method of controlling the same 有权
标题翻译：半导体集成电路及其控制方法
公开(公告)号：US07830188B2
公开(公告)日：2010-11-09
申请号：US12333173
申请日：2008-12-11
申请人： Kyoung-Nam Kim
发明人： Kyoung-Nam Kim
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , H03L7/0812
摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.
摘要翻译：半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来使能或禁止更新使能信号，以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。

25. 发明申请

US20100278004A1 ADDRESS RECEIVING CIRCUIT FOR A SEMICONDUCTOR APPARATUS 有权
标题翻译：地址接收电路用于半导体器件
公开(公告)号：US20100278004A1
公开(公告)日：2010-11-04
申请号：US12834429
申请日：2010-07-12
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C8/06
CPC分类号： G11C8/06
摘要： An address receiving circuit for a semiconductor apparatus includes a controller that, in response to a semiconductor apparatus initialization-related command, generates a control signal having an activation cycle corresponding to the standard of cycle time of the semiconductor apparatus initialization-related command, and an address buffer that receives an address according to the control signal.
摘要翻译：一种用于半导体装置的地址接收电路包括控制器，响应于半导体装置初始化命令，产生具有对应于半导体装置初始化命令的周期时间标准的激活周期的控制信号，以及地址缓冲器，根据控制信号接收地址。

26. 发明授权

US07515482B2 Pipe latch device of semiconductor memory device 有权
标题翻译：半导体存储器件的锁闩装置
公开(公告)号：US07515482B2
公开(公告)日：2009-04-07
申请号：US11477384
申请日：2006-06-30
申请人： Kyoung-Nam Kim , Ho-Youb Cho
发明人： Kyoung-Nam Kim , Ho-Youb Cho
IPC分类号： G11C7/00
CPC分类号： G11C19/28 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/222 , G11C11/4076 , G11C11/4096
摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.
摘要翻译：管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

27. 发明申请

US20080165591A1 Semiconductor memory device and method for driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20080165591A1
公开(公告)日：2008-07-10
申请号：US11819803
申请日：2007-06-29
申请人： Kyoung-Nam Kim , Yoon-Jae Shin
发明人： Kyoung-Nam Kim , Yoon-Jae Shin
IPC分类号： G11C7/00 , G11C7/10 , G11C8/00
CPC分类号： G11C7/22 , G11C7/02 , G11C7/222
摘要： A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL clocks and outputting a frequency-modulated DLL clock in response to the modulation control signal; and a data strobe signal generator for outputting the frequency-modulated DLL clock as a data strobe signal.
摘要翻译：半导体存储器件包括：调制控制器，用于产生用于控制频率调制操作的调制控制信号; 延迟锁定环（DLL）电路，用于执行延迟锁定操作以产生第一和第二DLL时钟并响应于调制控制信号输出调频DLL时钟; 以及数据选通信号发生器，用于输出调频DLL时钟作为数据选通信号。

28. 发明授权

US07345949B2 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US07345949B2
公开(公告)日：2008-03-18
申请号：US11325937
申请日：2005-12-30
申请人： Kyoung-Nam Kim , Sang-Hee Kang
发明人： Kyoung-Nam Kim , Sang-Hee Kang
IPC分类号： G11C8/00
CPC分类号： G11C7/1072
摘要： A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the column active sense pulse, for dividing a clock signal by N to thereby output a divided clock signal, N being a positive integer greater than 1; a plurality of shift registers connected in series and synchronized with the divided clock signal, wherein each shift register transmits the column active sense pulse to the next shift register; and a column active control signal generator for logically combining outputs of the shift registers to thereby generate a column active control signal.
摘要翻译：本发明的同步半导体存储器件包括：操作控制器，用于响应于列地址和列命令信号而输出列主动检测脉冲; 移位寄存器控制器，响应于列主动检测脉冲被激活，用于将时钟信号除以N，从而输出分频时钟信号，N是大于1的正整数; 多个移位寄存器串联连接并与分频时钟信号同步，其中每个移位寄存器将列活动检测脉冲发送到下一个移位寄存器; 以及列活动控制信号发生器，用于逻辑地组合移位寄存器的输出，从而生成列活动控制信号。

29. 发明授权

US07339847B2 BLEQ driving circuit in semiconductor memory device 有权
标题翻译： BLEQ驱动电路在半导体存储器件中
公开(公告)号：US07339847B2
公开(公告)日：2008-03-04
申请号：US11709745
申请日：2007-02-23
申请人： Kyoung-Nam Kim , Kang-Seol Lee
发明人： Kyoung-Nam Kim , Kang-Seol Lee
IPC分类号： G11C7/12
CPC分类号： G11C11/4094
摘要： A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply voltage, a BLEQ driver for generating the equalization signal by using the second boosted voltage in response to an equalization command and providing the equalization signal to a precharge unit, an equalizer and an I/O switch module. By using the second boosted voltage VPUP, which is lower than a first boosted voltage and higher than the supply voltage, as the equalization signal to be provided to gates of transistors for precharging a low power device to a precharge voltage level, it is possible to save current that a voltage pump consumes and satisfy a constant tRP.
摘要翻译：用于产生用于在半导体存储器件中执行预充电操作的均衡信号的位线均衡信号（BLEQ）驱动电路包括：第二升压电压发生器，用于通过泵送电源电压产生第二升压电压; BLEQ驱动器，用于产生均衡信号，并且将均衡信号提供给预充电单元，均衡器和I / O开关模块。通过使用低于第一升压电压并高于电源电压的第二升压电压VPUP作为要提供给用于将低功率器件预充电到预充电电压电平的晶体管的栅极的均衡信号，节省电压泵消耗并满足一定tRP的电流。

30. 发明授权

US07102938B2 Internal voltage generation control circuit and internal voltage generation circuit using the same 有权
标题翻译：内部电压发生控制电路和使用其的内部电压发生电路
公开(公告)号：US07102938B2
公开(公告)日：2006-09-05
申请号：US11102420
申请日：2005-04-08
申请人： Sang Hee Kang , Kyoung-Nam Kim
发明人： Sang Hee Kang , Kyoung-Nam Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C5/147 , G11C7/12 , G11C11/4094
摘要： An internal voltage generation control circuit and an internal voltage generation circuit using the same are provided. The internal voltage generation control circuit comprises first to n-th latches and a logic unit. The first latch receives, as an input signal, a column active pulse signal generated after a read/write command is input, and latches state information of the column active pulse signal, received when a clock signal is enabled, during a predetermined time, and then outputs the latched information. A k-th latch (2≦k≦n) receives an output signal of a k−1-th latch, and latches state information of the output signal of the k−1-th latch, received when the clock signal is enabled, during a predetermined time, and then outputs the latched information. The logic unit performs a logical operation between the column active pulse signal and output signals of the n latches and outputs an internal voltage generation control signal.
摘要翻译：提供内部电压产生控制电路和使用其的内部电压产生电路。内部电压产生控制电路包括第一至第n锁存器和逻辑单元。第一锁存器作为输入信号接收在输入读/写命令之后产生的列有效脉冲信号，并且在预定时间期间锁存在启用时钟信号时接收的列活动脉冲信号的状态信息，以及然后输出锁存信息。第k个锁存器（2 <= k <= n）接收第k-1个锁存器的输出信号，并且锁存当时钟信号为时钟信号时接收到的第k-1个锁存器的输出信号的状态信息在预定时间内启用，然后输出锁存信息。逻辑单元执行列活动脉冲信号和n个锁存器的输出信号之间的逻辑运算，并输出内部电压产生控制信号。

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