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21. 发明授权

US09087565B2 Pre-charging a data line 有权
标题翻译：预充电数据线
公开(公告)号：US09087565B2
公开(公告)日：2015-07-21
申请号：US13793815
申请日：2013-03-11
申请人： Annie-Li-Keow Lum , Derek C. Tao
发明人： Annie-Li-Keow Lum , Derek C. Tao
IPC分类号： G11C7/00 , G11C7/12 , G11C7/10 , G11C11/419
CPC分类号： G11C11/419 , G11C7/1048 , G11C7/12
摘要： A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.
摘要翻译：控制电路包括数据驱动器，充电电路和与数据驱动器和充电电路耦合的第一数据线。所述充电电路被配置为当所述第一数据线被选择用于对与所述第一数据线相对应的存储单元进行访问时对所述第一数据线进行充电，并且当所述第一数据线未被选择用于访问所述存储器单元时，。基于第一控制信号的数据驱动器被配置为将第一数据线上的信号传送到数据驱动器的输出。

22. 发明申请

US20120020176A1 GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS 有权
标题翻译：生成和放大差分信号
公开(公告)号：US20120020176A1
公开(公告)日：2012-01-26
申请号：US12839575
申请日：2010-07-20
申请人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
发明人： Chung-Ji Lu , Hung-Jen Liao , Cheng Hung Lee , Derek C. Tao , Annie-Li-Keow Lum , Hong-Chen Cheng
IPC分类号： G11C7/06 , H03F3/45
CPC分类号： G11C7/067 , G11C7/065
摘要： Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain.
摘要翻译：一些实施例涉及一种电路，包括：具有第一左漏极，第一左栅极和第一左源的第一左晶体管; 第二左晶体管，具有第二左漏极，第二左栅极和第二左源极; 第三左晶体管，具有第三左漏极，第三左栅极和第三左源; 第一右晶体管，具有第一右漏极，第一右栅极和第一右源; 第二右晶体管，具有第二右漏极，第二右栅极和第二右源; 第三右晶体管，具有第三右漏极，第三右栅极和第三右源; 左节点，电耦合第一左排水口，第二左排水管，第二左闸门，第三右闸门和第三左排水管; 以及电连接第一右排水管，第二右排水管，第二右浇口，第三左浇口和第三右排水沟的右节点。

23. 发明授权

US08194495B2 Clock generators, memory circuits, systems, and methods for providing an internal clock signal 有权
标题翻译：时钟发生器，存储器电路，系统和用于提供内部时钟信号的方法
公开(公告)号：US08194495B2
公开(公告)日：2012-06-05
申请号：US12723077
申请日：2010-03-12
申请人： Derek C. Tao , Chung-Ji Lu , Annie-Li-Keow Lum
发明人： Derek C. Tao , Chung-Ji Lu , Annie-Li-Keow Lum
IPC分类号： G11C8/00
CPC分类号： G06F1/10 , G11C7/22 , G11C7/222 , G11C11/413
摘要： A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.
摘要翻译：时钟发生器包括第一输入端和第二输入端。第一输入端能够接收包括定义第一脉冲宽度的第一状态转变和第二状态转换的第一时钟信号。第二输入端能够接收具有第三状态转换的第二时钟信号。时间段从第一状态转换到第三状态转换。时钟发生器可以比较第一个脉冲宽度和时间周期。时钟发生器可以输出具有从第四状态转变到第五状态转变的第二脉冲宽度的第三时钟信号。根据第一脉冲宽度与时间段的比较，第三时钟信号的第五状态转换能够被第一时钟信号的第二状态转换或第二时钟信号的第三状态转换触发。

24. 发明授权

US07898875B2 Write assist circuit for improving write margins of SRAM cells 有权
标题翻译：写辅助电路，提高SRAM单元的写入裕度
公开(公告)号：US07898875B2
公开(公告)日：2011-03-01
申请号：US12253735
申请日：2008-10-17
申请人： Derek C. Tao , Annie-Li-Keow Lum , Chung-Ji Lu , Subramani Kengeri
发明人： Derek C. Tao , Annie-Li-Keow Lum , Chung-Ji Lu , Subramani Kengeri
IPC分类号： G11C7/10
CPC分类号： G11C11/413
摘要： A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.
摘要翻译：存储器电路包括存储器阵列，其还包括以行和列排列的多个存储单元; 多个第一位线，每个第一位线连接到存储器阵列的一列; 以及多个写入辅助锁存器，每个写入辅助锁存器连接到多个第一位线之一。多个写入辅助锁存器中的每一个被配置为增加多个第一位线中的一个连接上的电压。

25. 发明授权

US08643422B1 Slicer and method of operating the same 有权
标题翻译：切片机及其操作方法
公开(公告)号：US08643422B1
公开(公告)日：2014-02-04
申请号：US13547396
申请日：2012-07-12
申请人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Tsung-Ching Huang , Derek C. Tao
发明人： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen Chung , Chih-Chang Lin , Tsung-Ching Huang , Derek C. Tao
IPC分类号： H03K3/356
CPC分类号： H03K5/08 , H03K3/356139 , H04L27/01
摘要： This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.
摘要翻译：该描述涉及包括第一锁存器的限幅器。第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。第一时钟信号与第二时钟信号不同。第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

26. 发明授权

US08519444B2 Modified design rules to improve device performance 有权
标题翻译：改进设计规则以提高设备性能
公开(公告)号：US08519444B2
公开(公告)日：2013-08-27
申请号：US12879447
申请日：2010-09-10
申请人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
发明人： Annie Lum , Derek C. Tao , Cheng Hung Lee , Chung-Ji Lu , Hong-Chen Cheng , Vineet Kumar Agrawal , Keun-Young Kim , Pyong Yun Cho
IPC分类号： H01L27/118
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L27/0207 , H01L27/088 , Y02P90/265
摘要： The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.
摘要翻译：上述布局，装置结构和方法利用虚设装置将边缘结构和/或非允许结构的扩散区域扩展到虚设装置。这种扩散区域的扩展可解决或减少LOD和边缘效应问题。此外，在边缘装置旁边处理伪装置的栅极结构也仅允许在虚设装置旁边添加一个虚拟结构，并将该不动产保存在半导体芯片上。虚拟设备被禁用，其性能不重要。因此，利用虚设装置根据设计规则扩展边缘结构和/或非允许结构的扩散区域允许分辨率或降低或LOD和边缘效应发生，而不会降低成品率或增加布局面积。

27. 发明授权

US08406078B2 Memory circuits having a plurality of keepers 有权
标题翻译：存储电路具有多个保持器
公开(公告)号：US08406078B2
公开(公告)日：2013-03-26
申请号：US13025668
申请日：2011-02-11
申请人： Annie Lum , Derek C. Tao , Young Seog Kim
发明人： Annie Lum , Derek C. Tao , Young Seog Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C5/147 , G11C11/412 , G11C11/413
摘要： A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
摘要翻译：存储电路包括以列方式设置的第一多个存储器阵列。存储器电路包括第一多个保持器，每个保持器与第一多个存储器阵列中的对应的一个存储器阵列电耦合。第一限流器与第一多个保持器电耦合并共享。第一多个扇区开关各自在第一限流器和第一多个保持器中的相应一个之间电耦合。

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