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21. 发明授权

US07403965B2 Encryption/decryption system for calculating effective lower bits of a parameter for Montgomery modular multiplication 有权
标题翻译：加密/解密系统，用于计算Montgomery模数乘法的参数的有效低位
公开(公告)号：US07403965B2
公开(公告)日：2008-07-22
申请号：US10888991
申请日：2004-07-13
申请人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
发明人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
IPC分类号： G06F7/00
CPC分类号： G06F7/728
摘要： An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND, the parameter ND satisfying R×R−1−N×ND=1 for an integer N and a radix R that is coprime to and greater than N, with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.
摘要翻译：一种用于蒙哥马利模乘的运算装置，其快速计算参数ND，对于整数N满足RxR ^{-1 -NxND = 1的参数ND和与N并且大于N的基数R，大量有效的低位。该装置包括ND发生器，乘积累加（MAC）运算符和和数据存储。 ND发生器以每个时钟周期的k比特的速率产生有效的低位，参考变量S的低k位，以及降低奇数正整数N的k位。MAC算子将所产生的 k位ND值乘以N，并将所得到的乘积加到S中。和数据存储器存储用MAC运算符的输出更新的变量S，其位被向右移位k位，供ND生成器使用在随后的时钟周期。}

22. 发明申请

US20050165876A1 Multiple-word multiplication-accumulation circuit and Montgomery modular multiplication-accumulation circuit 有权
标题翻译：多字乘法积累电路和蒙哥马利模积累电路
公开(公告)号：US20050165876A1
公开(公告)日：2005-07-28
申请号：US10898178
申请日：2004-07-26
申请人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
发明人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
IPC分类号： G06F7/52 , G06F7/544 , G06F7/72 , G09C1/00 , G06F7/38
CPC分类号： G06F7/728 , G06F7/5443
摘要： A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.
摘要翻译：适用于单端口存储器的多字乘法积累电路。该电路由乘积（MAC）运算符和周围寄存器组成。 MAC运算符具有不同位宽的乘法器和乘法器输入端口，以计算从存储器读出的多个字数据的乘积之和。这些寄存器用作缓冲存储多字数据以提供给MAC操作员的各个输入端口。调整在每个时钟周期内提供给MAC运算符的数据量，使得MAC运算符在一个时钟周期内消耗和产生的数据总量将等于或小于存储器可以传输的最大数据量一个时钟周期。该功能使得能够使用带宽限制的单端口存储器，而不会对MAC操作者使用的效率造成不利影响。

23. 发明申请

US20050165875A1 Arithmetic device 有权
标题翻译：算术设备
公开(公告)号：US20050165875A1
公开(公告)日：2005-07-28
申请号：US10888991
申请日：2004-07-13
申请人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
发明人： Kenji Mukaida , Masahiko Takenaka , Naoya Torii , Shoichi Masui
IPC分类号： G06F7/72 , G09C1/00 , G06F7/00
CPC分类号： G06F7/728
摘要： An arithmetic device for Montgomery modular multiplication which quickly calculates a parameter ND with a large number of effective lower bits. The device comprises an ND generator, a multiplication-accumulation (MAC) operator, and a sum data store. The ND generator produces effective lower bits of ND at a rate of k bits per clock cycle, with reference to lower k bits of a variable S, as well as to lower k bits of an odd positive integer N. The MAC operator multiplies the produced k-bit ND value by N and adds the resulting product to S. The sum data store stores the variable S, which is updated with the output of the MAC operator, with its bits shifted right by k bits, for use by the ND generator in the subsequent clock cycle.
摘要翻译：一种用于蒙哥马利模数乘法的运算装置，它可以快速计算具有大量有效低位的参数ND。该装置包括ND发生器，乘积累加（MAC）运算符和和数据存储。 ND发生器以每个时钟周期的k比特的速率产生有效的低位，参考变量S的低k位，以及降低奇数正整数N的k位。MAC算子将所产生的 k位ND值乘以N，并将所得到的乘积加到S中。和数据存储器存储用MAC运算符的输出更新的变量S，其位被向右移位k位，供ND生成器使用在随后的时钟周期。

24. 发明授权

US5838791A Encoder and decoder 失效
标题翻译：编码器和解码器
公开(公告)号：US5838791A
公开(公告)日：1998-11-17
申请号：US512909
申请日：1995-08-09
申请人： Naoya Torii , Noboru Iwayama , Masahiko Takenaka , Takayuki Hasebe , Masahiro Matsuda
发明人： Naoya Torii , Noboru Iwayama , Masahiko Takenaka , Takayuki Hasebe , Masahiro Matsuda
IPC分类号： H04N7/167 , G06F21/10 , G06T9/00 , G09C1/00 , G09C5/00 , H03M7/30 , H04L9/10 , H04N5/85 , H04N9/804 , H04N19/00 , H04N19/423 , H04N19/46 , H04N19/467 , H04N19/70 , H04N19/85 , H04N21/2343 , H04N21/236 , H04N21/61 , H04N7/64
CPC分类号： H04N7/1675 , G06T9/008 , H04N9/8042 , H04N5/85
摘要： The present invention was made in order to provide a technology capable of safely ciphering compressed and encoded image data irrespective of lines or media and carrying out a correct decoding operation without any shifts in the frames of ciphered moving pictures. Further, so as to prevent giving any means of encoding from comparison of image ciphered data and so as to generate totally different ciphered image data from the same data compressed images, a processing is executed not on an ECB mode but on such modes as CBC, CFB, OFB or the like. Moreover, as an initial vector, information different for frames included in a header, that is, time information from the start of an image or a frame sequential number, is used. In this way, even if compressed images within adjacent frames are accidentally the same, totally different ciphered data can be obtained.
摘要翻译：本发明是为了提供能够安全地加密压缩和编码的图像数据的技术，而不管线路或媒体如何，并且在加密的运动图像的帧中没有任何移位的情况下执行正确的解码操作。此外，为了防止从图像加密数据的比较中提供编码的任何手段，并且从相同的数据压缩图像生成完全不同的加密图像数据，不是在ECB模式下执行处理，而是在诸如CBC， CFB，OFB等。此外，作为初始向量，使用了包含在标题中的帧不同的信息，即，从图像开始或帧顺序号的时间信息。以这种方式，即使相邻帧内的压缩图像意外相同，也可以获得完全不同的加密数据。

25. 发明授权

US5761651A Software charging system and software data utilization permitting device 失效
标题翻译：软件充电系统和软件数据使用许可设备
公开(公告)号：US5761651A
公开(公告)日：1998-06-02
申请号：US490049
申请日：1995-06-13
申请人： Takayuki Hasebe , Naoya Torii , Noboru Iwayama , Masahiko Takenaka , Masahiro Matsuda
发明人： Takayuki Hasebe , Naoya Torii , Noboru Iwayama , Masahiko Takenaka , Masahiro Matsuda
IPC分类号： G06F1/00 , G06F21/10 , G06F21/12 , G06F21/14 , G06F21/60 , G06F21/62 , G06Q30/04 , G06Q30/06 , G06Q50/00 , G06F17/60
CPC分类号： G06Q30/06 , G06Q10/1091 , G06Q30/0283 , G06Q40/12 , G06Q10/109
摘要： A software charging system includes a utilization permitting device for giving permission to use a software storing medium storing ciphered programs or data (software); and an authorization center capable of communicating with the utilization permitting device for setting a utilizable amount, totalling utilization amounts and charging a user. The utilization permitting device includes: a utilization permission processing part having a clock for obtaining date and time data, and having a date and time data storing unit for storing obtained date and time data until obtaining next data and time data; and a utilization amount managing part for calculating a software utilization amount of an end user. A software utilization amount is managed based on the number of days at the utilization permission processing part.
摘要翻译：一种软件计费系统包括利用许可装置，用于允许使用存储加密程序或数据（软件）的软件存储介质; 以及能够与利用许可装置进行通信的授权中心，用于设定可利用量，合计使用量和对用户收费。利用许可装置包括：具有用于获取日期和时间数据的时钟的利用许可处理部分，并具有日期和时间数据存储单元，用于存储获得的日期和时间数据，直到获得下一个数据和时间数据; 以及用于计算最终用户的软件使用量的利用量管理部。基于利用许可处理部分的天数来管理软件使用量。

26. 发明授权

US06067640A System for management of software employing memory for processing unit with regulatory information, for limiting amount of use and number of backup copies of software 失效
标题翻译：用于管理使用具有监管信息的处理单元的存储器的软件的系统，用于限制软件的使用量和备份副本的数量
公开(公告)号：US06067640A
公开(公告)日：2000-05-23
申请号：US42794
申请日：1998-03-17
申请人： Ryota Akiyama , Naoya Torii
发明人： Ryota Akiyama , Naoya Torii
IPC分类号： G06F1/00 , G06F9/06 , G06F21/10 , G06F21/12 , G06F21/14 , G06Q10/00 , G06Q50/00 , G06Q50/26 , H02H3/05 , G06F11/30 , H03K19/003
CPC分类号： G06F21/10 , G06F21/105 , G06F2211/007 , G06F2221/2137
摘要： A set of a management-use memory medium in which is written various type of regulatory information (limit I of use of software, limit L of production of the next generation, a number K of generations showing up to what generation backup copies can be produced, software identification information PID, etc.) and a software memory medium in which the software is stored is established and use of the software is allowed under the restrictions of this regulatory information. Further, the software memory medium and the management-use memory medium may be provided in the same memory medium or the two may be constituted as separate memory media. In the case of the latter separate management system, the software is allowed to be used only when the software identification information PID written in the two match. It is therefore possible to suppress the unauthorized use of software without detracting from the spatial convenience of software use.
摘要翻译：一组管理用存储介质，其中写入了各种类型的监管信息（限制使用软件，限制下一代的生产，可以产生几代备份副本的K代数，软件识别信息PID等）和存储软件的软件存储介质，并且在该监管信息的限制下允许使用该软件。此外，软件存储介质和管理用存储介质可以设置在相同的存储介质中，或者两者可以构成为分离的存储介质。在后一种单独管理系统的情况下，只有当软件识别信息PID写在两个匹配中时才允许使用该软件。因此，可以在不损害软件使用的空间便利的情况下抑制未经授权的使用软件。

27. 发明授权

US07158638B2 Encryption circuit 有权
标题翻译：加密电路
公开(公告)号：US07158638B2
公开(公告)日：2007-01-02
申请号：US10034321
申请日：2002-01-03
申请人： Souichi Okada , Naoya Torii , Tomohiro Hayashi , Chikahiro Deguchi , Yumi Fujiwara
发明人： Souichi Okada , Naoya Torii , Tomohiro Hayashi , Chikahiro Deguchi , Yumi Fujiwara
IPC分类号： H04K1/04
CPC分类号： H04L9/0631 , H04L2209/122 , H04L2209/24
摘要： An encryption circuit that reduces a scale of circuit and can achieve a certain level of high-speed processing in the implementation of the AES block cipher. A round processing unit comprises: a first Round Key Addition circuit that adds a round key value to input data; an intermediate register/Shift Row transformation circuit that temporarily stores the output of the first Round Key Addition circuit and executes Shift Row transformation; a Byte Sub transformation circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which executes Byte Sub transformation; a second Round Key Addition circuit into which the values of the intermediate register/Shift Row transformation circuit are inputted and which adds round key values; a Mix Column transformation circuit that executes Mix Column transformation upon the outputs of the second Round Key Addition circuit; and a second selector that outputs to the second Round Key Addition circuit one of the outputs of a first selector, the intermediate register/Shift Row transformation circuit, the Byte Sub transformation circuit, and the Mix Column transformation circuit.
摘要翻译：一种减少电路规模的加密电路，可在实现AES块密码时实现一定程度的高速处理。圆处理单元包括：向输入数据添加循环密钥值的第一循环密钥加法电路; 中间寄存器/移位行变换电路，暂时存储第一循环密钥加法电路的输出，并执行移位行变换; 输入中间寄存器/移位行变换电路的值并执行Byte Sub变换的字节子变换电路; 第二循环密钥加法电路，其中输入中间寄存器/移位行变换电路的值，并加上循环键值; 混合列变换电路，对第二循环密钥加法电路的输出执行混合列变换; 以及第二选择器，其向第二圆形加法电路输出第一选择器，中间寄存器/移位行变换电路，字节子变换电路和混合列变换电路的输出之一。

28. 发明授权

US6118874A Encrypted data recovery method using split storage key and system thereof 失效
标题翻译：使用分割存储密钥及其系统的加密数据恢复方法
公开(公告)号：US6118874A
公开(公告)日：2000-09-12
申请号：US50066
申请日：1998-03-30
申请人： Eiji Okamoto , Masahiro Mambo , Seiichi Domyo , Hiroyoshi Tsuchiya , Tooru Kawai , Kazuo Takaragi , Naoya Torii , Takeshi Tanida
发明人： Eiji Okamoto , Masahiro Mambo , Seiichi Domyo , Hiroyoshi Tsuchiya , Tooru Kawai , Kazuo Takaragi , Naoya Torii , Takeshi Tanida
IPC分类号： G09C1/00 , H04L9/08 , H04L9/10 , H04L9/32
CPC分类号： H04L9/0894
摘要： When a secret is encrypted and stored, it is necessary to provide a countermeasure for the situation where a key is lost (key recovery system). In the present invention, a key recovery system for an enveloped data format in which a common key is used to encrypt a plaintext (secret) and a user's public key is used to encrypt the common key and attached to an encrypted text is provided. In the present invention, only the common key is decrypted to recover the secret without reconstruction of split secret keys kept in a plurality of key storage apparatuses.
摘要翻译：当秘密被加密和存储时，有必要为密钥丢失的情况（密钥恢复系统）提供对策。在本发明中，提供了一种使用公用密钥加密明文（秘密）和用户公钥的包络数据格式的密钥恢复系统，用于加密公用密钥并附加到加密文本。在本发明中，只有公用密钥被解密才能恢复密码，而不需要重新保存在多个密钥存储设备中的分离密钥。

29. 发明授权

US5325433A Encryption communication system 失效
标题翻译：加密通信系统
公开(公告)号：US5325433A
公开(公告)日：1994-06-28
申请号：US41453
申请日：1993-04-02
申请人： Naoya Torii , Takayuki Hasebe , Ryota Akiyama
发明人： Naoya Torii , Takayuki Hasebe , Ryota Akiyama
IPC分类号： G09C1/00 , H04L9/08 , H04L9/30 , H04L9/00
CPC分类号： H04L9/083 , H04L9/0863
摘要： An encryption communication system including: a communication center having at least a key information generating unit for generating key generating information used for encryption communication; and a plurality of user computers, each interconnected by a plurality of paths through the communication center, and each having at least an encryption key generating unit and an encryption processing unit. The communication center generates the key generating information Z based on predetermined modulo arithmetic formula. The user computer sends a password PW to the communication center, receives the key generating information therefrom, and generates an encryption key K used between the user computer and another party's computer based on predetermined modulo arithmetic formula. Further, the communication center provides a plurality of modulus numbers to share prime numbers assigned to at least two paths between the user computer and the other party's computer, and between the user computer and another party's computer, so that is possible to reduce the number of prime numbers.
摘要翻译：一种加密通信系统，包括：至少具有用于生成用于加密通信的密钥生成信息的密钥信息生成单元的通信中心; 以及多个用户计算机，每个用户计算机通过通信中心的多个路径互连，并且每个用户计算机至少具有加密密钥生成单元和加密处理单元。通信中心基于预定的模运算公式生成密钥生成信息Z。用户计算机向通信中心发送密码PW，从其接收密钥生成信息，并且基于预定的模运算公式生成在用户计算机与另一方的计算机之间使用的加密密钥K. 此外，通信中心提供多个模数，以共享分配给用户计算机和另一方的计算机之间的至少两条路径的质数，以及用户计算机与另一方的计算机之间的素数，使得可以减少质数。

30. 发明授权

US5313521A Key distribution protocol for file transfer in the local area network 失效
标题翻译：局域网文件传输的密钥分发协议
公开(公告)号：US5313521A
公开(公告)日：1994-05-17
申请号：US868571
申请日：1992-04-15
申请人： Naoya Torii , David B. Newman, Jr.
发明人： Naoya Torii , David B. Newman, Jr.
IPC分类号： G09C1/00 , H04L9/08
CPC分类号： H04L9/083 , H04L9/0822 , H04L9/321 , H04L9/3297
摘要： A cryptographic communications apparatus and method for use with a first terminal, a file server, a key distribution center and a communications channel. The method is made simple by using classical-key-encryption algorithms for electronic generation of session keys. The terminal is verified at a key distribution center, using time stamp and secret identification numbers. Each path is encrypted, with each encrypted message decoded at the key distribution center and file server.
摘要翻译：一种用于与第一终端，文件服务器，密钥分发中心和通信信道一起使用的密码通信装置和方法。该方法通过使用经典密钥加密算法进行电子生成会话密钥而变得简单。终端在密钥分发中心进行验证，使用时间戳和秘密识别号码。每个路径被加密，每个加密消息在密钥分发中心和文件服务器处解码。

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