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21. 发明申请

US20110242926A1 PSEUDO-INVERTER CIRCUIT ON SeO1 有权
标题翻译： PSO1上的PSEUDO-INVERTER电路
公开(公告)号：US20110242926A1
公开(公告)日：2011-10-06
申请号：US12793553
申请日：2010-06-03
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/08 , G05F1/10
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

22. 发明授权

US07919393B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US07919393B2
公开(公告)日：2011-04-05
申请号：US12769299
申请日：2010-04-28
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a structure that includes a relaxed or pseudo-relaxed layer on a substrate. The method includes the steps of growing an elastically stressed layer of semiconductor material on a donor substrate; forming a glassy layer of a viscous material on the stressed layer; removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate material; patterning the stressed layer; and heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer and form the relaxed or pseudo-relaxed layer of the structure.
摘要翻译：一种用于形成在衬底上包括松弛或假松弛层的结构的方法。该方法包括在施主衬底上生长半导体材料的弹性应力层的步骤; 在应力层上形成粘性材料的玻璃状层; 去除供体衬底的一部分以形成包括玻璃层，应力层和供体衬底材料的表面层的结构; 图案化应力层; 并且在至少玻璃质层的粘度温度的温度下对结构进行热处理，以使应力层松弛以形成结构的松弛或假松弛层。

23. 发明授权

US07736988B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US07736988B2
公开(公告)日：2010-06-15
申请号：US11345495
申请日：2006-02-02
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/76 , H01L21/30 , H01L21/46
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.
摘要翻译：描述了在衬底上形成松弛或假松弛有用层的方法。该方法包括在施主衬底上生长应变半导体层，通过在某一粘度温度下变得粘稠的材料的玻璃质层将接收器衬底接合到应变半导体层以形成第一结构。该方法还包括从第一结构分离施主衬底以形成包括接受衬底，玻璃体层和应变层的第二结构，然后在足够的温度和时间对第二结构进行热处理以使应变中的应变松弛并且在接收器基板上形成松弛或假松弛的有用层。

24. 发明授权

US07572714B2 Film taking-off method 有权
标题翻译：电影起飞方式
公开(公告)号：US07572714B2
公开(公告)日：2009-08-11
申请号：US11221045
申请日：2005-09-06
申请人： Cécile Aulnette , Ian Cayrefourcq , Carlos Mazure
发明人： Cécile Aulnette , Ian Cayrefourcq , Carlos Mazure
IPC分类号： H01L21/30
CPC分类号： H01L21/76254
摘要： The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the periphery of the wafer, with the step having a mean thickness that is less than that of the wafer; and selectively implanting atomic species through a face of the wafer but not through the step to form an implanted zone at a defined implant depth with the film being defined between the face of the wafer and the implanted zone. The implantation of atomic species into the step can be prevented by forming a protective layer at least over the step or by masking the step. The invention also relates to a wafer obtainable by the method.
摘要翻译：本发明涉及一种从初始晶片开始制造用于电子学，光学或光电子学中的薄膜的方法，其包括通过晶片的一个表面注入原子物质的步骤。该方法包括：形成围绕晶片周边的限定高度的台阶，其平均厚度小于晶片的平均厚度; 并且通过晶片的表面选择性地注入原子物质，但不通过该步骤，以在限定的注入深度处形成植入区域，其中膜被限定在晶片的表面和植入区域之间。可以通过至少在该步骤上形成保护层或通过掩蔽该步骤来防止将原子物质注入到该步骤中。本发明还涉及可通过该方法获得的晶片。

25. 发明授权

US07510949B2 Methods for producing a multilayer semiconductor structure 有权
标题翻译：多层半导体结构的制造方法
公开(公告)号：US07510949B2
公开(公告)日：2009-03-31
申请号：US11106135
申请日：2005-04-13
申请人： Carlos Mazure , Bruno Ghyselen
发明人： Carlos Mazure , Bruno Ghyselen
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259
摘要： Methods for producing a multilayer semiconductor structure are described. In an embodiment, the method includes providing a support substrate made of a first semiconductor material having a first lattice parameter, and depositing a layer of a second semiconductor material having a second lattice parameter, substantially different than the first, onto the support substrate to form an intermediate structure having an interface therebetween, the depositing being conducted such that most of the defects are confined to an adaptation layer located in a region adjacent to the interface. The method also includes creating a zone of weakness in the intermediate structure, bonding the second semiconductor material layer to a target substrate, detaching the support substrate at the zone to obtain a multilayer semiconductor structure having an exposed surface where detached, and fully removing the adaptation layer to obtain a relaxed thin layer of the second semiconductor material having a high quality surface.
摘要翻译：对多层半导体结构体的制造方法进行说明。在一个实施例中，该方法包括提供由具有第一晶格参数的第一半导体材料制成的支撑衬底，以及将具有与第一晶格参数基本上不同于第一晶格参数的第二半导体材料层沉积到支撑衬底上以形成其间具有界面的中间结构，所述沉积被导通，使得大部分缺陷被限制在位于与界面相邻的区域中的适配层。该方法还包括在中间结构中产生弱点区域，将第二半导体材料层粘合到目标基板上，在该区域分离支撑基板，以获得具有分离的暴露表面的多层半导体结构，并且完全去除适应以获得具有高质量表面的第二半导体材料的松弛薄层。

26. 发明申请

US20070264801A1 Semiconductor buffer structures 有权
标题翻译：半导体缓冲结构
公开(公告)号：US20070264801A1
公开(公告)日：2007-11-15
申请号：US11431336
申请日：2006-05-09
申请人： Nyles Cody , Chantal Arena , Pierre Tomasini , Carlos Mazure
发明人： Nyles Cody , Chantal Arena , Pierre Tomasini , Carlos Mazure
IPC分类号： H01L21/20
CPC分类号： C23C16/22 , C23C16/24 , C23C16/45523 , C30B25/165 , C30B29/52
摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
摘要翻译：通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。在形成渐变的SiGe缓冲层期间，SiGe从硅前体和锗前体的沉积被中断一次或多次，其中停止向硅衬底的硅前体的流动，同时锗前体流向保持底物。

27. 发明授权

US07115481B2 Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate 失效
标题翻译：用于同时产生至少一对半导体结构的方法，每个半导体结构在衬底上包括至少一个有用层
公开(公告)号：US07115481B2
公开(公告)日：2006-10-03
申请号：US10686084
申请日：2003-10-14
申请人： Bruno Ghyselen , Cécile Aulnette , Benoit Bataillou , Carlos Mazure , Hubert Moriceau
发明人： Bruno Ghyselen , Cécile Aulnette , Benoit Bataillou , Carlos Mazure , Hubert Moriceau
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , Y10S438/977
摘要： A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.
摘要翻译：一种用于同时产生至少一对半导体结构的方法，每个半导体结构在衬底上包括至少一个有用层。该方法包括提供初始结构，其包括在支撑衬底上具有正面的有用层。将原子物质植入有用层中至受控的平均植入深度，以形成限定第一和第二有用层的有用层内的弱点区域。接下来，将加强基板粘合到初始结构的正面。然后沿着弱化区从第二有用层分离第一有用层，以获得一对具有第一结构的半导体结构，该第一结构包括加强衬底和第一有用层，以及包括支撑衬底和第二有用层的第二结构。所获得的结构可用于电子学，光电子学或光学领域。

28. 发明授权

US07018909B2 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate 有权
标题翻译：在基材上包含松弛或假松弛层的成形结构
公开(公告)号：US07018909B2
公开(公告)日：2006-03-28
申请号：US10784016
申请日：2004-02-20
申请人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
发明人： Bruno Ghyselen , Carlos Mazure , Emmanuel Arene
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L21/76259 , H01L21/324 , H01L21/76254 , H01L2221/68363
摘要： The invention relates to methods of forming a relaxed or pseudo-relaxed layer on a substrate, wherein the relaxed layer may be a semiconductor material. An implementation of the method includes growing an elastically stressed semiconductor material layer on a donor substrate, forming a glassy layer of a viscous material and bonding it to the stressed layer, removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate, and then heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer. The glassy layer can also be bonded to a receiving substrate so that the structure can be transferred thereto. Implementations also relate to structures obtained from the method.
摘要翻译：本发明涉及在衬底上形成松弛或假松弛层的方法，其中松弛层可以是半导体材料。该方法的实现包括在施主衬底上生长弹性应力的半导体材料层，形成粘性材料的玻璃层并将其粘合到应力层，去除供体衬底的一部分以形成包括玻璃层的结构，应力层和供体衬底的表面层，然后在至少玻璃质层的粘度温度的温度下对结构进行热处理以使应力层松弛。玻璃状层也可以结合到接收基板，从而可以将结构转移到其上。实现也涉及从该方法获得的结构。

29. 发明申请

US20050191824A1 Methods for producing a multilayer semiconductor structure 有权
标题翻译：多层半导体结构的制造方法
公开(公告)号：US20050191824A1
公开(公告)日：2005-09-01
申请号：US11106135
申请日：2005-04-13
申请人： Carlos Mazure , Bruno Ghyselen
发明人： Carlos Mazure , Bruno Ghyselen
IPC分类号： H01L21/20 , H01L21/762 , H01L29/10 , H01L29/15 , H01L21/30 , H01L31/0312
CPC分类号： H01L29/1054 , H01L21/76254 , H01L21/76259
摘要： Methods for producing a multilayer semiconductor structure are described. In an embodiment, the method includes providing a support substrate made of a first semiconductor material having a first lattice parameter, and depositing a layer of a second semiconductor material having a second lattice parameter that is substantially different than the first lattice parameter onto the support substrate. In this manner, an intermediate structure is formed that has an interface between the first and second semiconductor materials, and the depositing is conducted such that most of the defects in the deposited layer are confined to an adaptation layer located in a region adjacent to the interface. The method also includes creating a zone of weakness in the intermediate structure, bonding the second semiconductor material layer to a target substrate, detaching the support substrate at the zone of weakness to obtain a multilayer semiconductor structure having an exposed surface where detached, and treating the exposed surface to assure that the adaptation layer is fully removed in order to obtain a relaxed thin layer of the second semiconductor material having a high quality surface.
摘要翻译：对多层半导体结构体的制造方法进行说明。在一个实施例中，该方法包括提供由具有第一晶格参数的第一半导体材料制成的支撑衬底，以及将具有与第一晶格参数基本不同的第二晶格参数的第二半导体材料层沉积到支撑衬底上。以这种方式，形成在第一和第二半导体材料之间具有界面的中间结构，并且进行沉积，使得沉积层中的大部分缺陷被限制在位于与界面相邻的区域中的适配层。该方法还包括在中间结构中产生弱点区域，将第二半导体材料层接合到目标衬底，在弱化区域分离支撑衬底以获得具有剥离的暴露表面的多层半导体结构，以确保适配层被完全去除以获得具有高质量表面的第二半导体材料的松弛薄层。

30. 发明授权

US5235203A Insulated gate field effect transistor having vertically layered elevated source/drain structure 失效
标题翻译：绝缘栅场效应晶体管具有垂直分层的源极/漏极结构
公开(公告)号：US5235203A
公开(公告)日：1993-08-10
申请号：US722416
申请日：1991-06-27
申请人： Carlos Mazure , Marius Orlowski , Matthew S. Noell
发明人： Carlos Mazure , Marius Orlowski , Matthew S. Noell
IPC分类号： H01L29/08
CPC分类号： H01L29/0847
摘要： An insulated gate field effect transistor having a vertically layered elevated source/drain structure includes an electrically conductive suppression region for resistance to hot carrier injection. The device includes a semiconductor substrate of first conductivity type having a gate insulator disposed on the surface of that substrate. A gate electrode, in turn, is disposed on the gate insulator. A lightly doped drain region of second conductivity type is formed in the substrate in alignment with the gate electrode. An electrically conductive suppression region having a first low electrical conductivity is positioned to electrically contact the drain region, but is electrically isolated from the gate electrode and is spaced a first distance from the gate electrode. A heavily doped drain contact also contacts the drain region and is spaced further away from the gate electrode than is the electrically conducted suppression region.
摘要翻译：具有垂直分层的升高的源/漏结构的绝缘栅场效应晶体管包括用于耐热载流子注入的导电抑制区。该器件包括第一导电类型的半导体衬底，其具有设置在该衬底表面上的栅极绝缘体。栅电极依次设置在栅极绝缘体上。第二导电类型的轻掺杂漏极区域与栅电极对准地形成在衬底中。具有第一低导电性的导电抑制区被定位成与漏极区电接触，但是与栅电极电隔离并且与栅电极隔开第一距离。重掺杂的漏极接触还接触漏极区，并且与导电抑制区相比更远离栅电极。

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