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21. 发明授权

US07702975B2 Integration of LBIST into array BISR flow 失效
标题翻译：将LBIST集成到数组BISR流中
公开(公告)号：US07702975B2
公开(公告)日：2010-04-20
申请号：US12099382
申请日：2008-04-08
申请人： Kevin W. Gorman , Michael R. Ouellette
发明人： Kevin W. Gorman , Michael R. Ouellette
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.
摘要翻译：用于集成电路结构的方法，集成电路结构和相关联的设计结构具有多个逻辑块，其中至少一个是冗余逻辑块。此外，该结构包括逻辑内置自检装置（LBIST），其可操作地连接到确定每个逻辑块的功能的逻辑块。存储器元件阵列包括在结构内并且可操作地连接到逻辑块。存储器元件中的至少一个包括冗余存储元件。该结构还包括可操作地连接到确定每个存储器元件的功能的存储器元件阵列的阵列内置自检器件（ABIST）。一个特征是使用可操作地连接到寄存器，逻辑块和存储器元件的单个控制器。单个控制器修复具有故障功能的逻辑块元素和具有故障功能的存储器元件。

22. 发明授权

US08839054B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

23. 发明授权

US08381052B2 Circuit and method for efficient memory repair 有权
标题翻译：电路和方法进行高效的内存修复
公开(公告)号：US08381052B2
公开(公告)日：2013-02-19
申请号：US12615856
申请日：2009-11-10
申请人： Valerie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette
发明人： Valerie H. Chickanosky , Kevin W. Gorman , Suzanne Granato , Michael R. Ouellette
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0401
摘要： A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
摘要翻译：一种用于测试存储器并为给定地址位置计算修复解决方案的电路和方法包括：在检测集成电路的故障存储器输出数据时暂停内置自检（BIST）操作。在暂停期间，电路和方法在n个周期内使用分析逻辑分析n个故障存储器输出数据组，并计算修复解决方案。正常操作可以恢复。

24. 发明授权

US07757141B2 Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry 有权
标题翻译：用于共享阵列内置自检（ABIST）电路的自动扩展寻址
公开(公告)号：US07757141B2
公开(公告)日：2010-07-13
申请号：US12055595
申请日：2008-03-26
申请人： Valerie H. Chickanosky , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Valerie H. Chickanosky , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译：一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。另外，该方法包括估计对应于被测试的最大总存储器地址大小的最高有效位的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享第一个比较树。

25. 发明申请

US20090251169A1 INTEGRATION OF LBIST INTO ARRAY BISR FLOW 失效
公开(公告)号：US20090251169A1
公开(公告)日：2009-10-08
申请号：US12099382
申请日：2008-04-08
申请人： Kevin W. Gorman , Michael R. Ouellette
发明人： Kevin W. Gorman , Michael R. Ouellette
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.

26. 发明授权

US08484543B2 Fusebay controller structure, system, and method 有权
标题翻译： Fusebay控制器结构，系统和方法
公开(公告)号：US08484543B2
公开(公告)日：2013-07-09
申请号：US13204929
申请日：2011-08-08
申请人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译：选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。每个状态机可以包括诸如“粘性位”的指示符，当其遇到类型的校正时可以被激活。指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。

27. 发明申请

US20130033951A1 STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A FUSEBAY 有权
标题翻译：将多个修复数据存入保险丝的结构和方法
公开(公告)号：US20130033951A1
公开(公告)日：2013-02-07
申请号：US13198894
申请日：2011-08-05
申请人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C29/785 , G11C29/802
摘要： Fuse macros of identical number of pages are serially arranged to form the same number of fusebay pages each having a length equal to the sum of the respective fuse macro page lengths. Each fuse macro has an enable latch configured to allow activation of one fuse macro at a time. A fusebay control device connected to a repair register may store data in and retrieve data from the fusebay. Next available fuse location is determined in programming mode so that data from a next repair pass may start where the last data ended.
摘要翻译：相同页数的保险丝宏串联地形成相同数量的保险丝页，每个保险丝页的长度等于相应的熔丝宏页面长度之和。每个保险丝宏都有一个使能锁存器，配置为允许一次激活一个保险丝宏。连接到维修寄存器的保险丝控制装置可以将数据存储在保险丝盒中并从熔丝座检索数据。在编程模式下确定下一个可用的熔丝位置，以便下一个维修通过的数据可以在最后一个数据结束的地方开始。

28. 发明授权

US08239715B2 Method and apparatus for a robust embedded interface 有权
标题翻译：强大的嵌入式接口的方法和装置
公开(公告)号：US08239715B2
公开(公告)日：2012-08-07
申请号：US12144686
申请日：2008-06-24
申请人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
发明人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
IPC分类号： G01R31/28
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译：提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。在测试模式下，数据由LSSD_C时钟启动。在功能模式下，数据由系统时钟（CLK）发送到RAM。还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。

29. 发明申请

US20110029827A1 METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST 审中-公开
标题翻译：用于建筑自检的方法，设备和设计结构
公开(公告)号：US20110029827A1
公开(公告)日：2011-02-03
申请号：US12511739
申请日：2009-07-29
申请人： VALERIE H CHICKANOSKY , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： VALERIE H CHICKANOSKY , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/14
摘要： In one embodiment, the invention is a method, apparatus, and design structure for built-in self-test for embedded memory in integrated circuit chips. One embodiment of a method for built-in self-test of an embedded memory includes setting up a plurality of test patterns at a speed of a test clock, where the speed of the test clock is slow enough for a tester to directly communicate with a chip in which the memory is embedded, and where the setting up includes loading a plurality of signal states used to communicate the test patterns to one or more components of a built-in self-test system, applying the test patterns to the embedded memory as a microburst at-speed, capturing output data from the embedded memory at-speed, the output data corresponding to only one of test patterns, and comparing the output data to expected data at the speed of the test clock.
摘要翻译：在一个实施例中，本发明是用于集成电路芯片中的嵌入式存储器的内置自检的方法，装置和设计结构。用于嵌入式存储器的内置自检的方法的一个实施例包括以测试时钟的速度设置多个测试图案，其中测试时钟的速度足够慢以使测试者直接与一个芯片，其中嵌入存储器，并且其中的设置包括将用于将测试图案传送到内置自检系统的一个或多个组件的多个信号状态，将测试图案作为高速微冲速，以速度从嵌入式存储器捕获输出数据，输出数据仅对应于测试模式之一，并且以测试时钟的速度将输出数据与期望数据进行比较。

30. 发明申请

US20090319841A1 STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE 有权
标题翻译：结构和装置用于强大的嵌入式界面
公开(公告)号：US20090319841A1
公开(公告)日：2009-12-24
申请号：US12144703
申请日：2008-06-24
申请人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
发明人： Steven M. Eustis , Kevin W. Gorman , David E. Lackey , Michael R. Ouellette
IPC分类号： G06F11/267 , G01R31/28 , G01R31/317
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译：设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于该数据将数据传播到数据处理单元。功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。

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