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21. 发明授权

US07821076B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07821076B2
公开(公告)日：2010-10-26
申请号：US12422278
申请日：2009-04-12
申请人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
发明人： Naozumi Morino , Atsushi Hiraiwa , Kazutoshi Oku , Toshiaki Ito , Motoshige Igarashi , Takayuki Sasaki , Masao Sugiyama , Hiroshi Yanagita , Shinichi Watarai
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L21/823892 , H01L27/0629 , H01L27/0928 , H01L2224/05554
摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.
摘要翻译：提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

22. 发明申请

US20080218224A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20080218224A1
公开(公告)日：2008-09-11
申请号：US12120090
申请日：2008-05-13
申请人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
发明人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
IPC分类号： H03L7/00
CPC分类号： H03K17/22
摘要： The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
摘要翻译：本发明旨在确保电源的初始状态，直到上电时电源电压稳定并且防止外部输入/输出缓冲电路的输出电路在设置时执行错误操作将预定的寄存器值等设置为初始值。电源检测电路输出表示从外部供给的电源电压进入预定状态的电源电压检测信号。上电复位电路接收电源电压检测信号，在预定定时指示内部电路的初始设定动作，并且响应于内部电路的初始设定动作的结束，改变外部输入输出缓冲电路从高阻抗状态到可操作状态。因此，当外部输入/输出缓冲电路变得可操作时，内部电路的初始设置已经完成。

23. 发明授权

US08698296B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08698296B2
公开(公告)日：2014-04-15
申请号：US12785488
申请日：2010-05-24
申请人： Naoto Taoka , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
发明人： Naoto Taoka , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
IPC分类号： H01L23/522 , H01L23/52 , H01L23/538
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3128 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06515 , H01L2224/1134 , H01L2224/13144 , H01L2224/14515 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/92247
摘要： The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
摘要翻译：要提高半导体器件的可靠性。具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流焊盘共同流动或不流动。第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。

24. 发明申请

US20100301466A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301466A1
公开(公告)日：2010-12-02
申请号：US12785488
申请日：2010-05-24
申请人： Naoto TAOKA , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
发明人： Naoto TAOKA , Atsushi Nakamura , Naozumi Morino , Toshikazu Ishikawa , Nobuhiro Kinoshita
IPC分类号： H01L23/522 , H01L23/52 , H01L23/538
CPC分类号： H01L24/81 , H01L21/563 , H01L23/3128 , H01L23/5226 , H01L23/5283 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05599 , H01L2224/06515 , H01L2224/1134 , H01L2224/13144 , H01L2224/14515 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48599 , H01L2224/49171 , H01L2224/49175 , H01L2224/4943 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2224/85 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2924/00 , H01L2224/92247
摘要： The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members).
摘要翻译：要提高半导体器件的可靠性。具有形成在其主表面上的多个焊盘的微计算机芯片（半导体芯片）以与芯片主表面相对的状态安装在布线基板的上表面上。耦合到形成在衬底上表面上的多个端子（接合引线）的焊盘包括多个第一焊盘，其中与流过其它焊盘的电流不同的独特电流流过多个第二焊盘，其中电流焊盘共同流动或不流动。第一焊盘或第二焊盘中的一个的另一个第一焊盘布置在第一焊盘的旁边。第一焊盘分别经由多个凸起（第一导电构件）电耦合到多个接合引线，而第二焊盘通过多个凸块（第二导电构件）接合到端子。

25. 发明授权

US07378887B2 Semiconductor integrated circuit with power-on state stabilization 有权
标题翻译：具有开机状态稳定的半导体集成电路
公开(公告)号：US07378887B2
公开(公告)日：2008-05-27
申请号：US11495735
申请日：2006-07-31
申请人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
发明人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
IPC分类号： H03L7/00
CPC分类号： H03K17/22
摘要： The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
摘要翻译：本发明旨在确保电源的初始状态，直到上电时电源电压稳定并且防止外部输入/输出缓冲电路的输出电路在设置时执行错误操作将预定的寄存器值等设置为初始值。电源检测电路输出表示从外部供给的电源电压进入预定状态的电源电压检测信号。上电复位电路接收电源电压检测信号，在预定定时指示内部电路的初始设定动作，并且响应于内部电路的初始设定动作的结束，改变外部输入输出缓冲电路从高阻抗状态到可操作状态。因此，当外部输入/输出缓冲电路变得可操作时，内部电路的初始设置已经完成。

26. 发明申请

US20070206781A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070206781A1
公开(公告)日：2007-09-06
申请号：US11651076
申请日：2007-01-09
申请人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
发明人： Takayuki Sasaki , Yasuto Igarashi , Naozumi Morino
IPC分类号： H04M1/76 , H04M7/00 , H04M9/00
CPC分类号： H04B3/32
摘要： A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered.
摘要翻译：减少半导体装置中的串扰噪声等外部噪声的影响的技术，以防止电路发生故障。易受噪声影响的真实信号线和条形信号线，以及电平移位器电路的输入信号线的一部分以及用于屏蔽这些信号线的屏蔽线布置在I / O单元上。这样的I / O单元被并排放置以完成真正的信号线连接和条形信号线连接。这些导线布置成通过多个I / O单元并且彼此平行或多层。

27. 发明申请

US20070046342A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20070046342A1
公开(公告)日：2007-03-01
申请号：US11495735
申请日：2006-07-31
申请人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
发明人： Naozumi Morino , Takahiro Irita , Yasuto Igarashi
IPC分类号： H03L7/00
CPC分类号： H03K17/22
摘要： The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
摘要翻译：本发明旨在确保电源的初始状态，直到上电时电源电压稳定并且防止外部输入/输出缓冲电路的输出电路在设置时执行错误操作将预定的寄存器值等设置为初始值。电源检测电路输出表示从外部供给的电源电压进入预定状态的电源电压检测信号。上电复位电路接收电源电压检测信号，在预定定时指示内部电路的初始设定动作，并且响应于内部电路的初始设定动作的结束，改变外部输入输出缓冲电路从高阻抗状态到可操作状态。因此，当外部输入/输出缓冲电路变得可操作时，内部电路的初始设置已经完成。

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