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21. 发明授权

US08367536B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08367536B2
公开(公告)日：2013-02-05
申请号：US13319739
申请日：2010-07-16
申请人： Hiroshi Watanabe , Naruhisa Miura
发明人： Hiroshi Watanabe , Naruhisa Miura
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1608 , H01L29/66068
摘要： The present invention includes steps below: (a) forming, on a drift layer, a first ion implantation mask and a second ion implantation mask individually by photolithography to form a third ion implantation mask, the first ion implantation mask having a mask region corresponding to a channel region and having a first opening corresponding to a source region, the second ion implantation mask being positioned in contact with an outer edge of the first ion implantation mask and configured to form a base region; (b) implanting impurities of a first conductivity type from the first opening with an ion beam using the third ion implantation mask to form a source region in an upper layer part of the silicon carbide drift layer; (c) removing the first ion implantation mask after the formation of the source region; and (d) implanting impurities of a second conductivity type with an ion beam from a second opening formed in the second ion implantation mask after the removal of the first ion implantation mask to form a base region deeper than the source region in the upper layer part of the drift layer.
摘要翻译：本发明包括以下步骤：（a）通过光刻法分别在漂移层上形成第一离子注入掩模和第二离子注入掩模，以形成第三离子注入掩模，第一离子注入掩模具有对应于沟道区，具有对应于源极区的第一开口，所述第二离子注入掩模定位成与所述第一离子注入掩模的外边缘接触并且被配置为形成基区; （b）使用第三离子注入掩模，用离子束从第一开口注入第一导电类型的杂质，以在碳化硅漂移层的上层部分中形成源极区; （c）在形成源极区域之后去除第一离子注入掩模; 以及（d）在除去第一离子注入掩模之后，从形成在第二离子注入掩模中的第二开口用离子束注入第二导电类型的杂质以形成比上层部分中的源极区更深的基极区的漂移层。

22. 发明授权

US08350309B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08350309B2
公开(公告)日：2013-01-08
申请号：US13310148
申请日：2011-12-02
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： G11C16/0483 , G11C16/10
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

23. 发明申请

US20120319762A1 POWER SWITCH 有权
标题翻译：开关;电源开关
公开(公告)号：US20120319762A1
公开(公告)日：2012-12-20
申请号：US13163110
申请日：2011-06-17
申请人： Hiroshi Watanabe , Hiroaki Kojima , Kazuya Machida
发明人： Hiroshi Watanabe , Hiroaki Kojima , Kazuya Machida
IPC分类号： G05F1/10
CPC分类号： H03K17/04123 , H03K17/04206 , H03K2217/0018 , H03K2217/0054
摘要： A method for switching between first and second voltages is provided. Initially, a first voltage is provided from a first input terminal to an output terminal through a first MOS transistor, and the first MOS transistor is deactivated. A back-gate of a second MOS transistor is shorted to the output terminal in response to the deactivation of the first MOS transistor and after a settling interval, and the second MOS transistor is activated while its back-gate is shorted to the terminal so as to provide a second voltage from a second input terminal to the output terminal.
摘要翻译：提供了用于在第一和第二电压之间切换的方法。首先，通过第一MOS晶体管从第一输入端子到输出端子提供第一电压，并且第一MOS晶体管被去激活。第二MOS晶体管的背栅极响应于第一MOS晶体管的去激活而在稳定间隔之后与输出端短路，并且第二MOS晶体管在其栅极与端子短路的同时被激活，从而以从第二输入端子向输出端子提供第二电压。

24. 发明申请

US20120299292A1 FLUID PASSAGE CONNECTING DEVICE AND REFRIGERATING CYCLE APPARATUS HAVING THE SAME 有权
标题翻译：流体连接装置和制冷循环装置
公开(公告)号：US20120299292A1
公开(公告)日：2012-11-29
申请号：US13474015
申请日：2012-05-17
申请人： Hiroshi Watanabe , Akihito Higashihara , Toshikazu Matsuda
发明人： Hiroshi Watanabe , Akihito Higashihara , Toshikazu Matsuda
IPC分类号： F16L19/00
CPC分类号： F16L23/22 , F16L41/086 , F25B41/003
摘要： A first component and a second component are connected with each other in a manner that a first passage of the first component and a second passage of the second component communicate with each other through a communication part. A seal component is disposed between the first component and the second component to provide a sealing between the first passage and the second passage. A ring component is arranged to surround the communication part, and is located adjacent to the communication part rather than the seal component. The ring component restricts the communication part from having an excess increase in a cross-sectional area.
摘要翻译：第一部件和第二部件以第一部件的第一通道和第二部件的第二通道通过连通部彼此连通的方式彼此连接。密封部件设置在第一部件和第二部件之间，以在第一通道和第二通道之间提供密封。环形部件布置成围绕通信部分，并且位于邻近通信部分而不是密封部件。环形部件限制了连通部分在横截面积上的过度增加。

25. 发明申请

US20120283270A1 EXTRACTS AND BEVERAGES CONTAINING 2,5-PIPERAZINEDIONE,3,6-BIS(PHENYLMETHYL)-, (3S,6S)- 审中-公开
标题翻译： 3,6-双（苯基甲基） - ，（3S，6S） - 酮的提取物和饮料包含2,5-二硝基苯
公开(公告)号：US20120283270A1
公开(公告)日：2012-11-08
申请号：US13516488
申请日：2010-02-26
申请人： Hideki Matsubayashi , Kenji Yamamoto , Hiroshi Watanabe , Lee Kian Hong
发明人： Hideki Matsubayashi , Kenji Yamamoto , Hiroshi Watanabe , Lee Kian Hong
IPC分类号： A61K31/495 , A61P25/00
CPC分类号： A61K38/12 , A23L2/52 , A23L2/66 , A23L13/30 , A23L33/10 , A23V2002/00 , A61K9/0095 , C07D241/08 , C07K5/06078 , A23V2250/204
摘要： The present invention aims to provide extracts or beverages containing 2,5-piperazinedione,3,6-bis(phenylmethyl)-,(3S,6S)—, which is a useful substance with an improving effect on learning motivation, in an easy-to-ingest form and at a high concentration. Extracts or beverages whose ratio between the content of 2,5-piperazinedione,3,6-bis(phenyl-methyl)-,(3S,6S)— (unit: μg/100 g) and Brix(Bx) is 6 (μg/100 g)/Bx or more can be ingested continuously over a long period of time as foods and beverages useful for improvement of learning motivation.
摘要翻译：本发明的目的是提供一种含有2,5-哌嗪二酮，3,6-双（苯基甲基） - ，（3S，6S） - 的提取物或饮料，其是有益物质，对学习动机具有改善的作用，以高浓度摄取形式。 2,5-哌嗪二酮，3,6-双（苯基甲基） - ，（3S，6S） - （单位：μg/ 100g）和白利糖度（Bx）含量之比为6（μg）的提取物或饮料 / 100克）/ Bx或以上可长期摄取，因为食品和饮料有助于改善学习动机。

26. 发明授权

US08295093B2 Multi-dot flash memory 有权
标题翻译：多点闪存
公开(公告)号：US08295093B2
公开(公告)日：2012-10-23
申请号：US12765478
申请日：2010-04-22
申请人： Takashi Ichikawa , Hiroshi Watanabe
发明人： Takashi Ichikawa , Hiroshi Watanabe
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/11551
摘要： A multi-dot flash memory set potentials of bit lines being disposed at a left side of a selected floating gate to V2(1)>V2(2)>V2(3)> . . . and set potentials of bit lines being disposed at a right side of the selected floating gate to V1(1)
摘要翻译：多点闪速存储器将位线的电位置于所选择的浮置栅极的左侧，以V2（1）> V2（2）> V2（3）>。。。并且将位线的电位设置在所选择的浮置栅极的右侧到V1（1）

27. 发明授权

US08227852B2 Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US08227852B2
公开(公告)日：2012-07-24
申请号：US11839156
申请日：2007-08-15
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： H01L29/788
CPC分类号： H01L29/4925 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A nonvolatile semiconductor memory includes a memory cell including, a semiconductor substrate, a first insulating layer on the semiconductor substrate, a floating gate on the first insulating layer, a second insulating layer on the floating gate, and a control gate electrode on the second insulating layer, wherein the floating gate is comprised a first conductive layer which is contact with the first insulating layer, a second conductive layer which is contact with the second insulating layer, and a semiconductor layer between the first and second conductive layers, and each of the first and second conductive layer is a metal layer or a silicide layer.
摘要翻译：非易失性半导体存储器包括：存储单元，包括半导体衬底，半导体衬底上的第一绝缘层，第一绝缘层上的浮置栅极，浮置栅极上的第二绝缘层，以及位于第二绝缘层上的控制栅电极层，其中所述浮栅包括与所述第一绝缘层接触的第一导电层，与所述第二绝缘层接触的第二导电层，以及所述第一和第二导电层之间的半导体层，第一和第二导电层是金属层或硅化物层。

28. 发明申请

US20120119685A1 POWER TRANSDUCER 有权
标题翻译：电力变压器
公开(公告)号：US20120119685A1
公开(公告)日：2012-05-17
申请号：US13357104
申请日：2012-01-24
申请人： Satoshi Ibori , Yoshihiro Uchino , Hiroshi Watanabe , Masahiro Hiraga
发明人： Satoshi Ibori , Yoshihiro Uchino , Hiroshi Watanabe , Masahiro Hiraga
IPC分类号： H02P3/12
CPC分类号： H02P3/22 , H02M1/32 , H02M5/458 , H02P3/14
摘要： The performance of a power transducer is improved while efficiently using a power semiconductor also by managing the permissible duty factor of the power semiconductor in the regenerative braking circuit provided in the power transducer. The user is allowed to set, through an operation panel provided on the power transducer, the resistance value of the regenerative braking resistor for thermally consuming the rotational energy generated during motor deceleration. The power transducer performs the steps of: calculating the current which flows in the regenerative braking circuit from the resistance value setting; obtaining the generation loss of the power semiconductor in the regenerative braking circuit with the calculated current value; and determining the permissible duty factor of the power semiconductor from the obtained generation loss.
摘要翻译：功率传感器的性能得到改善，同时通过管理设置在功率传感器中的再生制动电路中的功率半导体的允许占空比来有效地使用功率半导体。允许用户通过设置在功率传感器上的操作面板设置再生制动电阻器的电阻值，用于热消耗电动机减速期间产生的旋转能量。功率传感器执行以下步骤：从电阻值设定计算在再生制动电路中流动的电流; 以所计算的电流值获得再生制动电路中的功率半导体的发电损失; 以及从所获得的发电损失确定功率半导体的允许占空比。

29. 发明授权

US08174522B2 Three-dimensional (3D) structure data creation method, 3D structure data creation apparatus, computer-readable record media and computer system 有权
标题翻译：三维（3D）结构数据创建方法，3D结构数据创建装置，计算机可读记录介质和计算机系统
公开(公告)号：US08174522B2
公开(公告)日：2012-05-08
申请号：US12052198
申请日：2008-03-20
申请人： Hiroshi Watanabe
发明人： Hiroshi Watanabe
IPC分类号： G06T15/00
CPC分类号： G06F17/50
摘要： A three-dimensional (3D) structure data creation technique capable of readily creating 3D structure data is disclosed. This method is for producing data of a 3D structure which is made up of a plurality of elements. The method includes the steps of preparing first and second two-dimensional (2D) sectional images different in normal vector from each other, forming first and second unit graphics based on these 2D images, partitioning each unit graphic on a per-element basis, performing layout arrangement of two unit graphics in accordance with normal vectors, expanding these unit graphics for conversion to 3D objects, and allocating a selected element to a region in which elements of the unit graphics failing to coincide with each other, which region is included in and specified from those regions with intersection of respective partitioned parts of the unit graphics, thereby to create the 3D structure data required.
摘要翻译：公开了能够容易地创建3D结构数据的三维（3D）结构数据创建技术。该方法用于生成由多个元素构成的3D结构的数据。该方法包括以下步骤：在法向量中彼此不同的第一和第二二维（2D）截面图像，基于这些2D图像形成第一和第二单位图形，基于每个元素划分每个单位图形，执行根据法向量布置两个单位图形的布局布置，将这些单位图形扩展到3D对象，并将所选择的元素分配到单元图形的元素彼此不一致的区域，该区域包括在哪个区域中，从具有相应的单位图形的分割部分的区域指定，从而创建所需的3D结构数据。

30. 发明授权

US08084802B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US08084802B2
公开(公告)日：2011-12-27
申请号：US13025957
申请日：2011-02-11
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
摘要翻译：选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。第一级导电层具有接触区域。第二级导电层的部分被去除，位于接触区域上方。在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。

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