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21. 发明授权

US08084278B2 Method of manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：US08084278B2
公开(公告)日：2011-12-27
申请号：US12961868
申请日：2010-12-07
申请人： Yukio Uda , Koichi Sekiya , Kazuo Kobayashi , Yoichiro Tarui
发明人： Yukio Uda , Koichi Sekiya , Kazuo Kobayashi , Yoichiro Tarui
IPC分类号： H01L21/31
CPC分类号： H01L29/7802 , C23C16/325 , C23C16/56 , H01L21/046 , H01L22/12 , H01L29/0657 , H01L29/1608 , H01L29/66068 , Y10S438/931
摘要： A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF.
摘要翻译：将晶片WF安装在基板保持器中，并将基板保持器放置在成膜炉中。成膜炉通过真空泵通过气体排出部分排出，以尽可能完全地除去剩余的氧气。然后，将成膜炉中的温度在减压下加热至800℃至950℃的范围，同时通过气体引入部分引入诸如Ar或氦（He）的惰性气体。当温度达到该温度范围时，停止惰性气体的流入。通过气体导入部将蒸发的乙醇作为原料气体引入成膜炉，从而在晶片WF的整个表面上形成石墨膜。

22. 发明授权

US07564072B2 Semiconductor device having junction termination extension 有权
标题翻译：具有连接终端延伸的半导体器件
公开(公告)号：US07564072B2
公开(公告)日：2009-07-21
申请号：US11142322
申请日：2005-06-02
申请人： Kenichi Ohtsuka , Yoichiro Tarui , Yoshinori Matsuno , Kenichi Kuroda , Hiroshi Sugimoto
发明人： Kenichi Ohtsuka , Yoichiro Tarui , Yoshinori Matsuno , Kenichi Kuroda , Hiroshi Sugimoto
IPC分类号： H01L29/74
CPC分类号： H01L29/0619 , H01L29/1608 , H01L29/872 , Y10S388/917
摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.
摘要翻译：半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成比第一个p型区域。第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。第一p型区域的表面杂质浓度范围为1.8×1013〜4×1013cm-2，第二p型区域的表面杂质浓度为1×10 13〜2.5×10 13 cm -2。

23. 发明申请

US20060134847A1 Method of manufacturing a SiC vertical MOSFET 有权
标题翻译：制造SiC垂直MOSFET的方法
公开(公告)号：US20060134847A1
公开(公告)日：2006-06-22
申请号：US11353992
申请日：2006-02-15
申请人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi , Hiroshi Sugimoto , Tetsuya Takami
发明人： Yoichiro Tarui , Ken-ichi Ohtsuka , Masayuki Imaizumi , Hiroshi Sugimoto , Tetsuya Takami
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/265
CPC分类号： H01L29/7802 , H01L21/0465 , H01L21/047 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.
摘要翻译：提供了一种半导体器件及其制造方法，其中改善了沟道电阻和JFET电阻之间的折衷关系，从而改善了器件的小型化，并且通过离子注入使用相同的掩模形成源极区域和基极区域。在使用SiC的垂直MOSFET中，通过使用相同的锥形掩模的离子注入形成源极区域和基极区域，以使基极区域呈锥形。当锥形掩模的材料与离子注入中的SiC具有相同的范围时，锥形掩模的锥角设定为30°至60°，当锥形掩模的材料为SiO 2 。

24. 发明授权

US08587072B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08587072B2
公开(公告)日：2013-11-19
申请号：US13417755
申请日：2012-03-12
申请人： Yasunori Oritsuki , Naoki Yutani , Yoichiro Tarui
发明人： Yasunori Oritsuki , Naoki Yutani , Yoichiro Tarui
IPC分类号： H01L23/62 , H01L21/8238
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/1608 , H01L29/402 , H01L29/456 , H01L29/66068 , H01L29/7803 , H01L2924/0002 , H01L2924/00
摘要： An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.
摘要翻译： SiC半导体器件包括形成在SiC衬底中的半导体元件，源电极和通过使用其底表面上具有阻挡金属的互连层形成的栅极焊盘，以及通过使用部分势垒形成的温度测量电阻元件金属在互连线。

25. 发明授权

US08513763B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08513763B2
公开(公告)日：2013-08-20
申请号：US12820480
申请日：2010-06-22
申请人： Yoichiro Tarui
发明人： Yoichiro Tarui
IPC分类号： H01L29/47 , H01L23/544
CPC分类号： H01L29/872 , H01L23/544 , H01L29/0623 , H01L29/1608 , H01L29/66143 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： There was a problem that it was difficult to manufacture silicon carbide semiconductor devices with suppressed variations in characteristics without increasing the number of process steps. A silicon carbide semiconductor device according to the present invention includes an N type SiC substrate and an N type SiC epitaxial layer as a silicon carbide semiconductor substrate of a first conductivity type, a plurality of recesses intermittently formed in a surface of the N type SiC epitaxial layer, P type regions as second-conductivity-type semiconductor layers formed in the N type SiC epitaxial layer in the bottoms of the plurality of recesses, and a Schottky electrode selectively formed over the surface of the N type SiC epitaxial layer, wherein the plurality of recesses all have an equal depth.
摘要翻译：存在难以制造具有抑制的特性变化的碳化硅半导体器件而不增加工艺步骤数量的问题。根据本发明的碳化硅半导体器件包括N型SiC衬底和作为第一导电类型的碳化硅半导体衬底的N型SiC外延层，在N型SiC外延表面间断地形成的多个凹槽形成在多个凹部的底部的N型SiC外延层中的作为第二导电型半导体层的P型区域，以及选择性地形成在N型SiC外延层的表面上的肖特基电极，其中，的凹槽都具有相同的深度。

26. 发明申请

US20120302051A1 MANUFACTURING METHOD OF SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US20120302051A1
公开(公告)日：2012-11-29
申请号：US13355710
申请日：2012-01-23
申请人： Yoshinori MATSUNO , Yoichiro Tarui
发明人： Yoshinori MATSUNO , Yoichiro Tarui
IPC分类号： H01L21/329
CPC分类号： H01L29/1608 , H01L21/0465 , H01L21/0485 , H01L29/0615 , H01L29/0619 , H01L29/6606 , H01L29/872
摘要： A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
摘要翻译：通过干热氧化在外延层上形成氧化硅膜，在SiC衬底的背面上形成欧姆电极，在SiC衬底的欧姆电极和背面之间形成欧姆接头，退火SiC 衬底，除去氧化硅膜，在外延层上形成肖特基电极。然后，进行烧结处理以在肖特基电极和外延层之间形成肖特基结。

27. 发明授权

US08252672B2 Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same 有权
标题翻译：包含碳化硅层的碳化硅半导体器件及其制造方法
公开(公告)号：US08252672B2
公开(公告)日：2012-08-28
申请号：US12267040
申请日：2008-11-07
申请人： Tomokatsu Watanabe , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
发明人： Tomokatsu Watanabe , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
IPC分类号： H01L21/265
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0485 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A method of manufacturing a silicon carbide semiconductor device having a silicon carbide layer, the method including a step of implanting at least one of Al ions, B ions and Ga ions having an implantation concentration in a range not lower than 1E19 cm−3 and not higher than 1E21 cm−3 from a main surface of the silicon carbide layer toward the inside of the silicon carbide layer while maintaining the temperature of the silicon carbide layer at 175° C. or higher, to form a p-type impurity layer; and forming a contact electrode whose back surface establishes ohmic contact with a front surface of the p-type impurity layer on the front surface of the p-type impurity layer.
摘要翻译：一种制造具有碳化硅层的碳化硅半导体器件的方法，该方法包括以下步骤：注入注入浓度在1E19cm-3以上的Al离子，B离子和Ga离子中的至少一种，而不是高于1E21cm-3，从碳化硅层的主表面朝向碳化硅层的内部，同时将碳化硅层的温度保持在175℃以上，形成p型杂质层; 以及形成其背面与p型杂质层前表面上的p型杂质层的前表面欧姆接触的接触电极。

28. 发明申请

US20090250705A1 SILICON CARBIDE SEMICONDUCTOR DEVICE COMPRISING SILICON CARBIDE LAYER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：含有碳化硅层的硅碳化硅半导体器件及其制造方法
公开(公告)号：US20090250705A1
公开(公告)日：2009-10-08
申请号：US12267040
申请日：2008-11-07
申请人： Tomokatsu WATANABE , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
发明人： Tomokatsu WATANABE , Sunao Aya , Naruhisa Miura , Keiko Sakai , Shohei Yoshida , Toshikazu Tanioka , Yukiyasu Nakao , Yoichiro Tarui , Masayuki Imaizumi
IPC分类号： H01L29/24 , H01L21/34
CPC分类号： H01L29/7802 , H01L21/046 , H01L21/0485 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C. becomes lower than that in a case where the p++ region is formed by ion implantation at a temperature over 300° C. Further, this can avoid any process failure.
摘要翻译：碳化硅半导体器件的p基极欧姆接触由通过高浓度离子注入形成的p ++层和金属电极组成。由于在室温下进行的高浓度离子注入使p ++层的晶体显着降低，导致处理失败，所以使用在高温下注入的方法。在器件的开关损耗等方面，期望p基极欧姆接触的电阻率应该更低。在众所周知的技术中，在离子注入温度，欧姆接触电阻率和工艺故障之间的详细关系中没有提及。然后，在离子注入步骤中，碳化硅晶片的温度保持在175℃至300℃的范围内，更优选在175℃至200℃的范围内。在175℃〜300℃的温度范围内通过离子注入形成的p ++区域的p基极欧姆接触变得低于在超过300°的温度下通过离子注入形成p ++区域的情况下的p基极欧姆接触此外，这可以避免任何过程失败。

29. 发明授权

US09041007B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09041007B2
公开(公告)日：2015-05-26
申请号：US13299882
申请日：2011-11-18
申请人： Eisuke Suekawa , Yasunori Oritsuki , Yoichiro Tarui
发明人： Eisuke Suekawa , Yasunori Oritsuki , Yoichiro Tarui
IPC分类号： H01L29/06 , H01L29/861 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/16
CPC分类号： H01L29/7811 , H01L29/1608 , H01L29/45 , H01L29/456 , H01L29/4941 , H01L29/78 , H01L29/7802 , H01L29/7804 , H01L29/7815 , H01L29/861
摘要： A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n−-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.
摘要翻译：半导体器件的MOSFET单元包括形成在n漂移层的上部的多晶硅栅电极和n +源极区。层间绝缘膜覆盖栅电极。 Al源电极在层间绝缘膜上延伸。 Al栅极焊盘连接到栅电极。防止铝扩散的阻挡金属层插入在源电极和层间绝缘膜之间以及栅极焊盘和栅电极之间。

30. 发明授权

US08987817B2 Semiconductor device having a gate insulating film with a thicker portion covering a surface of an epitaxial protrusion and manufacturing method thereof 有权
标题翻译：具有覆盖外延突起的表面的较厚部分的栅极绝缘膜的半导体器件及其制造方法
公开(公告)号：US08987817B2
公开(公告)日：2015-03-24
申请号：US13197237
申请日：2011-08-03
申请人： Yoichiro Tarui
发明人： Yoichiro Tarui
IPC分类号： H01L29/66 , H01L29/78 , H01L23/544 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/08 , H01L29/16 , H01L29/167
CPC分类号： H01L29/7802 , H01L23/544 , H01L29/0657 , H01L29/0878 , H01L29/1608 , H01L29/167 , H01L29/41766 , H01L29/42368 , H01L29/66068 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of the present invention includes: a semiconductor substrate of a first conductive type; an epitaxial layer of the first conductive type formed on the semiconductor substrate and having a protrusion formed on a surface thereof; a well region of a second conductive type formed on the surface of the epitaxial layer at each side of the protrusion; a source region of the first conductive type selectively formed in a surface of the well region; a gate insulating film formed so as to cover at least the protrusion and the surface of the well region; and a gate electrode formed on a part of the gate insulating film corresponding to the protrusion. The gate insulating film is thicker in a region thereof corresponding to an upper surface of the protrusion than the other regions thereof.
摘要翻译：本发明的半导体器件包括：第一导电类型的半导体衬底; 所述第一导电类型的外延层形成在所述半导体衬底上并且在其表面上形成有突起; 形成在所述突起的每一侧的所述外延层的表面上的第二导电类型的阱区; 所述第一导电类型的源极区选择性地形成在所述阱区的表面中; 形成为至少覆盖所述阱区域的突起和表面的栅极绝缘膜; 以及形成在与所述突起相对应的所述栅极绝缘膜的一部分上的栅电极。栅极绝缘膜在与突起的上表面相对应的区域中比其他区域更厚。

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